# IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

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Displaying Results 1 - 25 of 35

Publication Year: 2006, Page(s):c1 - c4
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• ### IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

Publication Year: 2006, Page(s): c2
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• ### Improving Ariadne's Bundle by Following Multiple Threads in Abstraction Refinement

Publication Year: 2006, Page(s):2297 - 2316
Cited by:  Papers (9)
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The authors propose a scalable abstraction-refinement method for model checking invariant properties on large sequential circuits, which is based on fine-grain abstraction and simultaneous analysis of all abstract counterexamples of the shortest length. Abstraction efficiency is introduced to measure for a given abstraction-refinement algorithm how much of the concrete model is required to make th... View full abstract»

• ### An Algorithm for Synthesis of Reversible Logic Circuits

Publication Year: 2006, Page(s):2317 - 2330
Cited by:  Papers (165)  |  Patents (1)
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Reversible logic finds many applications, especially in the area of quantum computing. A completely specified n-input, n-output Boolean function is called reversible if it maps each input assignment to a unique output assignment and vice versa. Logic synthesis for reversible functions differs substantially from traditional logic synthesis and is currently an active area of research. The authors pr... View full abstract»

• ### Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping

Publication Year: 2006, Page(s):2331 - 2340
Cited by:  Papers (36)  |  Patents (15)
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In this paper, an iterative technology-mapping tool called IMap is presented. It supports depth-oriented (area is a secondary objective), area-oriented (depth is a secondary objective), and duplication-free mapping modes. The edge-delay model (as opposed to the more commonly used unit-delay model) is used throughout. Two new heuristics are used to obtain area reductions over previously published m... View full abstract»

• ### Vectorless Estimation of Maximum Instantaneous Current for Sequential Circuits

Publication Year: 2006, Page(s):2341 - 2352
Cited by:  Papers (15)
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Large current in a chip can cause problems such as noise and power consumption. In this paper, a vectorless approach to analyzing a tight upper bound on the maximum instantaneous current (MIC) of a circuit is proposed. Several types of signal correlations that can cause the MIC estimation to lose accuracy are first described. Next, taking signal correlations into account, theorems to identify gate... View full abstract»

• ### A High-Performance Subcircuit Recognition Method Based on the Nonlinear Graph Optimization

Publication Year: 2006, Page(s):2353 - 2363
Cited by:  Papers (3)
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Subcircuit recognition (SR) is a problem of identifying instances of a small subcircuit in a larger circuit. Despite recent progress toward linear optimization-based SR algorithms, finding a large set of subcircuits in a multimillion transistor or gate-level netlist may still be too slow for many integrated-circuit computer-aided design applications. This paper describes a new high-performance met... View full abstract»

• ### A Unified Theory of Timing Budget Management

Publication Year: 2006, Page(s):2364 - 2375
Cited by:  Papers (14)
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This paper presents a theoretical framework that solves optimally and in polynomial time many open problems in time budgeting. The approach unifies a large class of existing time-management paradigms. Examples include time budgeting for maximizing total weighted delay relaxation, minimizing the maximum relaxation, and min-skew time budget distribution. The authors develop a combinatorial framework... View full abstract»

• ### Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits

Publication Year: 2006, Page(s):2376 - 2392
Cited by:  Papers (12)  |  Patents (6)
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Uncertainty in circuit performance due to manufacturing and environmental variations is increasing with each new generation of technology. It is therefore important to predict the performance of a chip as a probabilistic quantity. This paper proposes three novel path-based algorithms for statistical timing analysis and parametric yield prediction of digital integrated circuits. The methods have be... View full abstract»

• ### On Constrained Pin-Mapping for FPGA&#8211;PCB Codesign

Publication Year: 2006, Page(s):2393 - 2401
Cited by:  Papers (3)
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Field-programmable gate arrays (FPGAs) are commonly used in board designs. The authors consider the constrained FPGA pin-mapping problem in the FPGA-printed circuit board (PCB) codesign process. Unlike all previous works, which only saw constrained FPGA pin mapping as an independent chip-level problem, they take into account the connectivity of the FPGA with other components on the PCB to minimize... View full abstract»

• ### Partitioning-Based Approach to Fast On-Chip Decoupling Capacitor Budgeting and Minimization

Publication Year: 2006, Page(s):2402 - 2412
Cited by:  Papers (13)  |  Patents (1)
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This paper proposes a fast decoupling capacitance (decap) allocation and budgeting algorithm for both early stage decap estimation and later stage decap minimization in today's very large scale integration physical design. The new method is based on a sensitivity-based conjugate gradient (CG) approach. But several new techniques that significantly improve the efficiency of the optimization process... View full abstract»

• ### Event-Driven Time-Domain Simulation of Closed-Loop Switched Circuits

Publication Year: 2006, Page(s):2413 - 2426
Cited by:  Papers (8)
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This paper addresses the accurate time-domain simulation of closed-loop switched circuits. It is known that for such systems, conventional analog simulation can be critical due to the presence of strongly nonlinear switching devices. In order to overcome the drawback, in this paper, an in-depth investigation of the weakness points of analog simulation is first presented. On the basis of the achiev... View full abstract»

• ### Delay Modeling and Statistical Design of Pipelined Circuit Under Process Variation

Publication Year: 2006, Page(s):2427 - 2436
Cited by:  Papers (10)
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Under inter-die and intra-die parameter variations, the delay of a pipelined circuit follows a statistical distribution. This paper presents analytical models to estimate yield for a pipelined design based on delay distributions of individual pipe stages. Using the proposed models, it is shown that a change in logic depth and an imbalance between stage yields can improve the design yield and the a... View full abstract»

• ### Correlation-Preserved Statistical Timing With a Quadratic Form of Gaussian Variables

Publication Year: 2006, Page(s):2437 - 2449
Cited by:  Papers (11)  |  Patents (2)
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A recent study shows that the existing first-order canonical timing model is not sufficient to represent the dependency of the gate/wire delay on the processing and operational variations when these variations become more and more significant. Due to nonlinear mapping from variation sources to the gate/wire delay, the distribution of the delay will no longer be Gaussian even if variation sources a... View full abstract»

• ### Defect Modeling Using Fault Tuples

Publication Year: 2006, Page(s):2450 - 2464
Cited by:  Papers (22)  |  Patents (1)
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Fault tuples represent a defect modeling mechanism capable of capturing the logical misbehavior of arbitrary defects in digital circuits. To justify this claim, this paper describes two types of logic faults (state transition and signal line faults) and formally shows how fault tuples can be used to precisely represent any number of faults of this kind. The capability of fault tuples to capture mi... View full abstract»

• ### Constraint-Driven Test Scheduling for NoC-Based Systems

Publication Year: 2006, Page(s):2465 - 2478
Cited by:  Papers (31)
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On-chip integrated network, the so-called network-on-chip (NoC), is becoming a promising communication paradigm for the next-generation embedded core-based system chips. The reuse of the on-chip network as test access mechanism has been recently proposed to handle the growing complexity of testing NoC-based systems. However, the NoC reuse is limited by the on-chip routing resources and various con... View full abstract»

• ### An Integrated High-Level On-Line Test Synthesis Tool

Publication Year: 2006, Page(s):2479 - 2491
Cited by:  Papers (5)  |  Patents (1)
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Several researchers have recently implemented on-line testability in the form of duplication-based self-checking digital system design, early in the design process. The authors consider the on-line testability within the optimization phase of iterative, cost function-driven high-level synthesis, such that self-checking resources are inserted automatically without any modification of the source beh... View full abstract»

• ### Improved$n$-Detection Test Sequences Under Transparent Scan

Publication Year: 2006, Page(s):2492 - 2501
Cited by:  Papers (1)
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The quality of test sequences for scan circuits under a test-application scheme called transparent scan as n-detection test sequences is studied. A transparent-scan sequence T is obtained from a compact single-detection combinational test set C. It is shown that for the same number of clock cycles required to apply C, the transparent-scan sequence T detects faults more times than C. It is also not... View full abstract»

• ### Thermal-Safe Test Scheduling for Core-Based System-on-Chip Integrated Circuits

Publication Year: 2006, Page(s):2502 - 2512
Cited by:  Papers (36)
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Overheating has been acknowledged as a major problem during the testing of complex system-on-chip integrated circuits. Several power-constrained test-scheduling solutions have been recently proposed to tackle this problem during system integration. However, we show that these approaches cannot guarantee hot-spot-free test schedules because they do not take into account the nonuniform distribution ... View full abstract»

• ### IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults

Publication Year: 2006, Page(s):2513 - 2525
Cited by:  Papers (7)
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An interconnect diagnosis scheme based on the oscillation ring (OR) test methodology for systems-on-chip (SOC) design with heterogeneous cores is proposed. In addition to traditional stuck-at and open faults, the OR test can also detect and diagnose important interconnect faults such as delay faults and crosstalk glitches. The large number of test rings in the SOC design, however, significantly co... View full abstract»

• ### A Framework for Automatic Design Validation of RTL Circuits Using ATPG and Observability-Enhanced Tag Coverage

Publication Year: 2006, Page(s):2526 - 2538
Cited by:  Papers (7)  |  Patents (5)
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This paper presents a framework for high-level design validation using an efficient register-transfer level (RTL) automatic test pattern generator (ATPG). The RTL ATPG algorithm first generates a test environment for each validation objective, which includes variable assignments, conditional statements, and arithmetic expressions in the hardware description language (HDL) description. The test env... View full abstract»

• ### An Approach to Placement-Coupled Logic Replication

Publication Year: 2006, Page(s):2539 - 2551
Cited by:  Papers (3)
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This paper presents a set of techniques for placement-coupled timing-driven logic replication. Two components are at the core of the approach. First, is an algorithm for optimal timing-driven fanin tree embedding; the algorithm is very general in that it can easily incorporate complex objective functions (e.g., placement costs) and can perform embedding on any graph-based target. Second, the repli... View full abstract»

• ### I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design

Publication Year: 2006, Page(s):2552 - 2556
Cited by:  Papers (3)
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Input-output (I/O) placement has always been a concern in modern integrated circuit design. Due to flip-chip technology, I/O can be placed throughout the whole chip without long wires from the periphery of the chip. However, because of I/O placement constraints in design cost (DC) and performance, I/O buffer planning becomes a pressing problem. During the early stages of circuits and package co-de... View full abstract»

• ### Efficient Static Compaction Techniques for Sequential Circuits Based on Reverse-Order Restoration and Test Relaxation

Publication Year: 2006, Page(s):2556 - 2564
Cited by:  Papers (4)
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The authors present efficient reverse-order-restoration (ROR)-based static test compaction techniques for synchronous sequential circuits. Unlike previous ROR techniques that rely on vector-by-vector fault-simulation-based restoration of test subsequences, the authors' technique restores test sequences based on efficient test relaxation. The restored test subsequence can be either concatenated to ... View full abstract»

• ### Exact and Heuristic Approaches to Input Vector Control for Leakage Power Reduction

Publication Year: 2006, Page(s):2564 - 2571
Cited by:  Papers (12)  |  Patents (2)
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Leakage power consumption is an increasingly serious problem in very large-scale integration circuits, especially for portable applications. Two novel approaches to leakage power minimization in static complementary metal-oxide-semiconductor circuits that employ input vector control (IVC) are investigated. The authors model leakage effects by means of pseudo-Boolean functions. These functions are ... View full abstract»

## Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

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## Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu