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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 11 • Date Nov. 2006

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Displaying Results 1 - 25 of 35
  • Table of contents

    Publication Year: 2006 , Page(s): c1 - c4
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Publication Year: 2006 , Page(s): c2
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  • Improving Ariadne's Bundle by Following Multiple Threads in Abstraction Refinement

    Publication Year: 2006 , Page(s): 2297 - 2316
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (794 KB)  

    The authors propose a scalable abstraction-refinement method for model checking invariant properties on large sequential circuits, which is based on fine-grain abstraction and simultaneous analysis of all abstract counterexamples of the shortest length. Abstraction efficiency is introduced to measure for a given abstraction-refinement algorithm how much of the concrete model is required to make the decision. The fully automatic techniques presented in this paper can efficiently reach or come near to the maximal abstraction efficiency. First, a fine-grain abstraction approach is given to keep the abstraction granularity small by breaking down large combinational logic cones with Boolean network variables (BNVs) and then treating both state variables and BNVs as atoms in abstraction. Second, a refinement algorithm is proposed based on an improved Ariadne's bundle In the legend of Theseus, Ariadne's bundle contained one ball of thread to help Theseus navigate the labyrinth. In this paper, we work with multiple threads-hence, the "improved." of synchronous onion rings on the abstract model, through which the transitions contain all shortest abstract counterexamples. The synchronous onion rings are exploited in two distinct ways to provide global guidance to the abstraction refinement process. The scalability of our algorithm is ensured in the sense that all the analysis and computation required in our refinement algorithm are conducted on the abstract model. Finally, we derive sequential don't cares from the invisible variables and use them to constrain the behavior of the abstract model. We conducted experimental comparisons of our new method with various existing techniques. The results show that our method outperforms other counterexample-guided methods in terms of both run time and abstraction efficiency View full abstract»

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  • An Algorithm for Synthesis of Reversible Logic Circuits

    Publication Year: 2006 , Page(s): 2317 - 2330
    Cited by:  Papers (71)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (537 KB)  

    Reversible logic finds many applications, especially in the area of quantum computing. A completely specified n-input, n-output Boolean function is called reversible if it maps each input assignment to a unique output assignment and vice versa. Logic synthesis for reversible functions differs substantially from traditional logic synthesis and is currently an active area of research. The authors present an algorithm and tool for the synthesis of reversible functions. The algorithm uses the positive-polarity Reed-Muller expansion of a reversible function to synthesize the function as a network of Toffoli gates. At each stage, candidate factors, which represent subexpressions common between the Reed-Muller expansions of multiple outputs, are explored in the order of their attractiveness. The algorithm utilizes a priority-based search tree, and heuristics are used to rapidly prune the search space. The synthesis algorithm currently targets the generalized n-bit Toffoli gate library. However, other algorithms exist that can convert an n-bit Toffoli gate into a cascade of smaller Toffoli gates. Experimental results indicate that the authors' algorithm quickly synthesizes circuits when tested on the set of all reversible functions of three variables. Furthermore, it is able to quickly synthesize all four-variable and most five-variable reversible functions that were in the test suite. The authors also present results for some benchmark functions widely discussed in literature and some new benchmarks that the authors have developed. The algorithm is shown to synthesize many, but not all, randomly generated reversible functions of as many as 16 variables with a maximum gate count of 25 View full abstract»

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  • Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping

    Publication Year: 2006 , Page(s): 2331 - 2340
    Cited by:  Papers (22)  |  Patents (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (521 KB) |  | HTML iconHTML  

    In this paper, an iterative technology-mapping tool called IMap is presented. It supports depth-oriented (area is a secondary objective), area-oriented (depth is a secondary objective), and duplication-free mapping modes. The edge-delay model (as opposed to the more commonly used unit-delay model) is used throughout. Two new heuristics are used to obtain area reductions over previously published methods. The first heuristic predicts the effects of various mapping decisions on the area of the final solution, and the second heuristic bounds the depth of the mapping solution at each node. In depth-oriented mode, when targeting five lookup tables (LUTs), IMap obtains depth optimal solutions that are 44.4%, 19.4%, and 5% smaller than those produced by FlowMap, CutMap, and DAOMap, respectively. Targeting the same LUT size in area-oriented mode, IMap obtains solutions that are 17.5% and 9.4% smaller than those produced by duplication-free mapping and ZMap, respectively. IMap is also shown to be highly efficient. Runtime improvements of between 2.3times and 82times are obtained over existing algorithms when targeting five LUTs. Area and runtime results comparing IMap to the other mappers when targeting four and six LUTs are also presented View full abstract»

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  • Vectorless Estimation of Maximum Instantaneous Current for Sequential Circuits

    Publication Year: 2006 , Page(s): 2341 - 2352
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (397 KB) |  | HTML iconHTML  

    Large current in a chip can cause problems such as noise and power consumption. In this paper, a vectorless approach to analyzing a tight upper bound on the maximum instantaneous current (MIC) of a circuit is proposed. Several types of signal correlations that can cause the MIC estimation to lose accuracy are first described. Next, taking signal correlations into account, theorems to identify gates that switch mutually exclusively are proposed. In particular, the proposed algorithm can naturally consider signal correlations across sequential elements (flip-flops), whereas previous research on this topic addressed combinational circuits only. After deriving the information of mutually exclusive switching, a graph algorithm is applied to obtain an upper bound on the MIC. On average, the obtained sequential benchmark results are 179% tighter than those from the iMax algorithm and 66% tighter than those from the partial input enumeration algorithm View full abstract»

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  • A High-Performance Subcircuit Recognition Method Based on the Nonlinear Graph Optimization

    Publication Year: 2006 , Page(s): 2353 - 2363
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (259 KB) |  | HTML iconHTML  

    Subcircuit recognition (SR) is a problem of identifying instances of a small subcircuit in a larger circuit. Despite recent progress toward linear optimization-based SR algorithms, finding a large set of subcircuits in a multimillion transistor or gate-level netlist may still be too slow for many integrated-circuit computer-aided design applications. This paper describes a new high-performance method to identify subcircuits using a nonlinear graph optimization strategy. The method uses an advanced nonlinear technique to find a global minimum of the objective function associated with the SR problem. Unlike linear graph optimization, this method does not approximate the objective function by the first-order terms in its Taylor series expansion. In contrast, to increase the recognition rate, the second-order terms are exploited to form a set of nonlinear equations that describe the net and device match probabilities. Consequently, computing the match probabilities in the new approach is based on the nonlocal structure of connections between nets and devices. An iterative nonlinear version of the Kaczmarz method (KM) is used to solve the obtained set of nonlinear equations. The KM efficiency is improved by making an important modification in its updating scheme, which leads to fast and stable convergence of the recognition process. The experimental results show that the new method is on average three times faster than linear graph optimization algorithms such as the probabilistic match assignment algorithm View full abstract»

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  • A Unified Theory of Timing Budget Management

    Publication Year: 2006 , Page(s): 2364 - 2375
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (576 KB) |  | HTML iconHTML  

    This paper presents a theoretical framework that solves optimally and in polynomial time many open problems in time budgeting. The approach unifies a large class of existing time-management paradigms. Examples include time budgeting for maximizing total weighted delay relaxation, minimizing the maximum relaxation, and min-skew time budget distribution. The authors develop a combinatorial framework through which we prove that many of the time-management problems can be transformed into a min-cost flow problem instance. The methodology is applied to intellectual-property-based datapath synthesis targeting field-programmable gate arrays. The synthesis flow maps the input operations to parameterized library modules during which different time budgeting policies have been applied. The techniques always improve the area requirement of the implemented test benches and consistently outperform a widely used competitor. The experiments verify that combining fairness and maximization objectives improves the results further as compared with pure maximum budgeting. The combined fairness and maximization objective improves the area by 25.8% and 28.7% in slice and LUT counts, respectively View full abstract»

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  • Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits

    Publication Year: 2006 , Page(s): 2376 - 2392
    Cited by:  Papers (7)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (534 KB)  

    Uncertainty in circuit performance due to manufacturing and environmental variations is increasing with each new generation of technology. It is therefore important to predict the performance of a chip as a probabilistic quantity. This paper proposes three novel path-based algorithms for statistical timing analysis and parametric yield prediction of digital integrated circuits. The methods have been implemented in the context of the EinsTimer static timing analyzer. The three methods are complementary in that they are designed to target different process variation conditions that occur in practice. Numerical results are presented to study the strengths and weaknesses of these complementary approaches. Timing analysis results in the face of statistical temperature and Vdd variations are presented on an industrial ASIC part on which a bounded timing methodology leads to surprisingly wrong results View full abstract»

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  • On Constrained Pin-Mapping for FPGA–PCB Codesign

    Publication Year: 2006 , Page(s): 2393 - 2401
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (258 KB) |  | HTML iconHTML  

    Field-programmable gate arrays (FPGAs) are commonly used in board designs. The authors consider the constrained FPGA pin-mapping problem in the FPGA-printed circuit board (PCB) codesign process. Unlike all previous works, which only saw constrained FPGA pin mapping as an independent chip-level problem, they take into account the connectivity of the FPGA with other components on the PCB to minimize the occurrence of net crossover and the PCB wirelength when computing a pin mapping. They propose an efficient tool, the versatile input/output (VIO) mapper, to automatically generate a proper pin-mapping upfront during the FPGA-PCB codesign process. Their input/output (I/O) mapper has a high level of flexibility. It can handle the different kinds of complex restrictions found in different FPGA devices. And it allows the PCB designers to lock down, say, the pin assignments for some critical signals before generating the assignments for the rest of the signals. Their mapper is based on an elegant 0-1 integer linear program (ILP) formulation. They show that due to the effective control of the number of integer variables and the use of a strong formulation (instead of an alternative weak formulation), their ILP-based approach is highly efficient in practice. It runs much faster than the mapping tool in Altera's Quartus II tool suite. In addition, they experimentally showed that the industrial tool's mapping algorithm is very far from optimal. For many instances on which Quartus II failed, feasible I/O mappings were found using the VIO mapper View full abstract»

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  • Partitioning-Based Approach to Fast On-Chip Decoupling Capacitor Budgeting and Minimization

    Publication Year: 2006 , Page(s): 2402 - 2412
    Cited by:  Papers (11)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (386 KB) |  | HTML iconHTML  

    This paper proposes a fast decoupling capacitance (decap) allocation and budgeting algorithm for both early stage decap estimation and later stage decap minimization in today's very large scale integration physical design. The new method is based on a sensitivity-based conjugate gradient (CG) approach. But several new techniques that significantly improve the efficiency of the optimization process were adopted. First, an efficient search step scheme to replace the time-consuming line search phase in the conventional CG method for decap budget optimization was proposed. Second, instead of optimizing an entire large circuit, the circuit is partitioned into a number of smaller subcircuits and optimized separately by exploiting the locality of adding decaps. Third, the time-domain merged adjoint method was applied to compute the sensitivity information and show that the partitioning-based merged adjoint method leads to better results than the flat merged adjoint method with the improved search scheme. Experimental results show that the proposed algorithm achieves at least ten times speed-up over similar decap allocation methods reported so far with similar budget quality, and a power grid circuit with about one million nodes can be optimized using the new method in half an hour on the latest Linux workstations View full abstract»

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  • Event-Driven Time-Domain Simulation of Closed-Loop Switched Circuits

    Publication Year: 2006 , Page(s): 2413 - 2426
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (382 KB) |  | HTML iconHTML  

    This paper addresses the accurate time-domain simulation of closed-loop switched circuits. It is known that for such systems, conventional analog simulation can be critical due to the presence of strongly nonlinear switching devices. In order to overcome the drawback, in this paper, an in-depth investigation of the weakness points of analog simulation is first presented. On the basis of the achieved understanding, a novel accurate and efficient simulation technique that combines conventional analog simulation with a suited event-driven management of internally controlled commutations is presented. The proposed method employs a novel algorithm for locating commutation time instants and a regionwise evaluation of critical switching devices. The method is general and can be easily inserted into analog simulator tools View full abstract»

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  • Delay Modeling and Statistical Design of Pipelined Circuit Under Process Variation

    Publication Year: 2006 , Page(s): 2427 - 2436
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (679 KB) |  | HTML iconHTML  

    Under inter-die and intra-die parameter variations, the delay of a pipelined circuit follows a statistical distribution. This paper presents analytical models to estimate yield for a pipelined design based on delay distributions of individual pipe stages. Using the proposed models, it is shown that a change in logic depth and an imbalance between stage yields can improve the design yield and the area of a pipeline a circuit. A novel statistical methodology is developed to enhance yield of a pipelined circuit under an area constraint. Based on the concept of area borrowing, the results show that incorporating a proper imbalance among stage areas in a four-stage pipeline improves design yield up to 15.4% for the same area (and reduces area up to 8.4% under a yield constraint) compared with a balanced design View full abstract»

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  • Correlation-Preserved Statistical Timing With a Quadratic Form of Gaussian Variables

    Publication Year: 2006 , Page(s): 2437 - 2449
    Cited by:  Papers (10)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (626 KB) |  | HTML iconHTML  

    A recent study shows that the existing first-order canonical timing model is not sufficient to represent the dependency of the gate/wire delay on the processing and operational variations when these variations become more and more significant. Due to nonlinear mapping from variation sources to the gate/wire delay, the distribution of the delay will no longer be Gaussian even if variation sources are normally distributed. A novel "quadratic timing model" is proposed to capture the nonlinearity of the dependency of gate/wire delays and arrival times on the variation sources. Systematic methodology is also developed to evaluate the correlation and distribution of the quadratic timing model. Based on these, a statistical static timing analysis algorithm that retains the complete correlation information during timing analysis and has linear computation complexity with respect to both the circuit size and the number of variation sources is proposed. Tested on the ISCAS circuits, the proposed algorithm shows significant accuracy improvement over the existing first-order algorithm with a small amount of computational cost View full abstract»

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  • Defect Modeling Using Fault Tuples

    Publication Year: 2006 , Page(s): 2450 - 2464
    Cited by:  Papers (18)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (801 KB) |  | HTML iconHTML  

    Fault tuples represent a defect modeling mechanism capable of capturing the logical misbehavior of arbitrary defects in digital circuits. To justify this claim, this paper describes two types of logic faults (state transition and signal line faults) and formally shows how fault tuples can be used to precisely represent any number of faults of this kind. The capability of fault tuples to capture misbehaviors beyond logic faults is then illustrated using many examples of varying degree of complexity. In particular, the ability of fault tuples to modulate fault controllability and observability is examined. Finally, it is described how fault tuples can and have been used to enhance testing tasks such as fault simulation, test generation, and diagnosis, and enable new capabilities such as interfault collapsing and application-based quality metrics View full abstract»

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  • Constraint-Driven Test Scheduling for NoC-Based Systems

    Publication Year: 2006 , Page(s): 2465 - 2478
    Cited by:  Papers (16)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (439 KB) |  | HTML iconHTML  

    On-chip integrated network, the so-called network-on-chip (NoC), is becoming a promising communication paradigm for the next-generation embedded core-based system chips. The reuse of the on-chip network as test access mechanism has been recently proposed to handle the growing complexity of testing NoC-based systems. However, the NoC reuse is limited by the on-chip routing resources and various constraints. Therefore, efficient test-scheduling methods are required to deliver feasible test time while meeting all the constraints. In this paper, the authors propose a comprehensive approach to test scheduling in NoC-based systems. The proposed scheduling algorithm is based on the use of dedicated routing path that is suitable for nonpreemptive test. The algorithm is improved by incorporating both preemptive and nonpreemptive tests. In addition, BIST, precedence, and power constraints were taken into consideration. Experimental results for the ITC'02 system-on-chip benchmarks show that the nonpreemptive scheduling based on dedicated path can efficiently reduce test application time compared to previous work, and the improved method provides a practical solution to the real-world NoC-based-system testing with both preemptive and nonpreemptive cores. It is also shown that various constraints can be incorporated to deliver a comprehensive test solution View full abstract»

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  • An Integrated High-Level On-Line Test Synthesis Tool

    Publication Year: 2006 , Page(s): 2479 - 2491
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1090 KB) |  | HTML iconHTML  

    Several researchers have recently implemented on-line testability in the form of duplication-based self-checking digital system design, early in the design process. The authors consider the on-line testability within the optimization phase of iterative, cost function-driven high-level synthesis, such that self-checking resources are inserted automatically without any modification of the source behavioral hardware description language code. This is enabled by introducing a metric for the on-line testability. A new variation of duplication (namely inversion testing) is also proposed and used, providing the system with an additional degree of freedom for minimizing hardware overheads associated with test resource insertion. Considering the on-line testability within the synthesis process facilitates fast and painless design space exploration, resulting in a versatile high-level-synthesis process, capable of producing alternative realizations according to the designer's directions, for alternative target technologies. Finally, the fault escape probability of the overall scheme is discussed theoretically and evaluated experimentally View full abstract»

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  • Improved n -Detection Test Sequences Under Transparent Scan

    Publication Year: 2006 , Page(s): 2492 - 2501
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (384 KB) |  | HTML iconHTML  

    The quality of test sequences for scan circuits under a test-application scheme called transparent scan as n-detection test sequences is studied. A transparent-scan sequence T is obtained from a compact single-detection combinational test set C. It is shown that for the same number of clock cycles required to apply C, the transparent-scan sequence T detects faults more times than C. It is also noted that a transparent-scan sequence based on a combinational test set contains unspecified values. The effects of specifying the unspecified values of the transparent-scan sequence on the quality of the sequence are studied by considering a random specification of these values. A procedure for modifying the scan-select subsequence of a (fully specified) transparent-scan sequence so as to improve its quality as an n-detection test sequence is also described. Finally, the extension of a transparent-scan test sequence into an n-detection test sequence that detects every target fault at least n times is considered. The results show a slower increase in test-application time with n than when combinational test sets are considered View full abstract»

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  • Thermal-Safe Test Scheduling for Core-Based System-on-Chip Integrated Circuits

    Publication Year: 2006 , Page(s): 2502 - 2512
    Cited by:  Papers (21)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (418 KB) |  | HTML iconHTML  

    Overheating has been acknowledged as a major problem during the testing of complex system-on-chip integrated circuits. Several power-constrained test-scheduling solutions have been recently proposed to tackle this problem during system integration. However, we show that these approaches cannot guarantee hot-spot-free test schedules because they do not take into account the nonuniform distribution of heat dissipation across the die and the physical adjacency of simultaneously active cores. This paper proposes a new test-scheduling approach that is able to produce short test schedules and guarantee thermal safety at the same time. Two thermal-safe test-scheduling algorithms are proposed. The first algorithm computes an exact (shortest) test schedule that is guaranteed to satisfy a given maximum temperature constraint. The second algorithm is a heuristic intended for complex systems with a large number of embedded cores, for which the exact thermal-safe test-scheduling algorithm may not be feasible. Based on a low-complexity test-session thermal-cost model, this algorithm produces near-optimal length test schedules with significantly less computational effort compared to the optimal algorithm View full abstract»

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  • IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults

    Publication Year: 2006 , Page(s): 2513 - 2525
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (650 KB) |  | HTML iconHTML  

    An interconnect diagnosis scheme based on the oscillation ring (OR) test methodology for systems-on-chip (SOC) design with heterogeneous cores is proposed. In addition to traditional stuck-at and open faults, the OR test can also detect and diagnose important interconnect faults such as delay faults and crosstalk glitches. The large number of test rings in the SOC design, however, significantly complicates the interconnect diagnosis problem. In this paper, the diagnosability of an interconnect structure is first analyzed then a fast diagnosability checking algorithm and an efficient diagnosis ring generation algorithm are proposed. It is shown in this paper that the generation algorithm achieves the maximum diagnosability for any interconnect. Two optimization techniques are also proposed, an adaptive and a concurrent diagnosis method, to improve the efficiency and effectiveness of interconnect diagnosis. Experiments on the MCNC benchmark circuits show the effectiveness of the proposed diagnosis algorithms. In all experiments, the method achieves 100% fault detection coverage and the optimal interconnect diagnosis resolution View full abstract»

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  • A Framework for Automatic Design Validation of RTL Circuits Using ATPG and Observability-Enhanced Tag Coverage

    Publication Year: 2006 , Page(s): 2526 - 2538
    Cited by:  Papers (4)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (519 KB) |  | HTML iconHTML  

    This paper presents a framework for high-level design validation using an efficient register-transfer level (RTL) automatic test pattern generator (ATPG). The RTL ATPG algorithm first generates a test environment for each validation objective, which includes variable assignments, conditional statements, and arithmetic expressions in the hardware description language (HDL) description. The test environment for a given validation objective is a set of symbolic conditions that allow for full controllability and observability of that objective. After the RTL ATPG terminates, a back-end translator intelligently translates the test environments into validation vectors by filling in the necessary values. Since the observability of error effect is naturally handled by the RTL ATPG algorithm, this approach is superior to most existing validation methods, which only focus on the excitation of HDL constructs. A set of heuristics is proposed to utilize high-level circuit information to enhance the RTL ATPG algorithm and to maximize the validation efficiency. The RTL ATPG algorithm is also coupled with an improved RTL validation-coverage metric, which can help users to gain a higher degree of confidence on the quality of generated validation vectors. The usage of the coverage metric also results in the generation of compact vector sets. Experimental results on academic and industrial benchmark circuits demonstrate that our method is able to obtain very high design-error coverage in short execution times View full abstract»

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  • An Approach to Placement-Coupled Logic Replication

    Publication Year: 2006 , Page(s): 2539 - 2551
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (431 KB) |  | HTML iconHTML  

    This paper presents a set of techniques for placement-coupled timing-driven logic replication. Two components are at the core of the approach. First, is an algorithm for optimal timing-driven fanin tree embedding; the algorithm is very general in that it can easily incorporate complex objective functions (e.g., placement costs) and can perform embedding on any graph-based target. Second, the replication tree is introduced, which allows to induce large fanin trees from a given circuit, which can then be optimized by the embedder. The authors have built an optimization engine around these two ideas and report promising results for the field-programmable gate array (FPGA) domain including clock period reductions of up to 36% compared with a timing-driven placement from versatile place and route (VPR) (Marquardt , 2000) and almost double the average improvement of local replication (Beraudo and Lillis, 2003). These results are achieved with modest area and runtime overhead. In addition, issues that arise due to reconvergence in the circuit specification are addressed. The authors build on the replication tree idea and enhance the timing-driven fanin tree embedding algorithm to optimize subcritical paths, yielding even better delay improvements View full abstract»

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  • I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design

    Publication Year: 2006 , Page(s): 2552 - 2556
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (350 KB) |  | HTML iconHTML  

    Input-output (I/O) placement has always been a concern in modern integrated circuit design. Due to flip-chip technology, I/O can be placed throughout the whole chip without long wires from the periphery of the chip. However, because of I/O placement constraints in design cost (DC) and performance, I/O buffer planning becomes a pressing problem. During the early stages of circuits and package co-design, I/O layout should be evaluated to optimize DC and to avoid product failures. The objective of this brief is to improve the existing/initial standard cell placement by I/O clustering, considering DC reduction and signal integrity preservation. The authors formulate it as a minimum cost flow problem that minimizes alphaW+betaD, where W is the I/O wirelength of the placement and D is the total voltage drop in the power network and, at the same time, reduces the number of I/O buffer blocks. The experimental results on some Microelectronics Center of North Carolina benchmarks show that the author's method averagely achieves better timing performance and over 32% DC reduction when compared with a conventional rule-of-thumb design that is popularly used by circuit designers View full abstract»

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  • Efficient Static Compaction Techniques for Sequential Circuits Based on Reverse-Order Restoration and Test Relaxation

    Publication Year: 2006 , Page(s): 2556 - 2564
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (397 KB) |  | HTML iconHTML  

    The authors present efficient reverse-order-restoration (ROR)-based static test compaction techniques for synchronous sequential circuits. Unlike previous ROR techniques that rely on vector-by-vector fault-simulation-based restoration of test subsequences, the authors' technique restores test sequences based on efficient test relaxation. The restored test subsequence can be either concatenated to the compacted test sequence, as in previous approaches, or merged with it. Furthermore, it allows the removal of redundant vectors from the restored subsequences using a state traversal technique and incorporates schemes for increasing the fault coverage of restored test subsequences to achieve an overall higher level of compaction. In addition, test relaxation is used to take ROR out of saturation. Experimental results demonstrate the effectiveness of the proposed techniques View full abstract»

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  • Exact and Heuristic Approaches to Input Vector Control for Leakage Power Reduction

    Publication Year: 2006 , Page(s): 2564 - 2571
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (300 KB) |  | HTML iconHTML  

    Leakage power consumption is an increasingly serious problem in very large-scale integration circuits, especially for portable applications. Two novel approaches to leakage power minimization in static complementary metal-oxide-semiconductor circuits that employ input vector control (IVC) are investigated. The authors model leakage effects by means of pseudo-Boolean functions. These functions are linearized and incorporated into an exact (optimal) integer linear programming (ILP) model, called virtual-gate ILP, which analyzes leakage variation with respect to a circuit's input vectors. A heuristic mixed-integer linear programming (MLP) method is also proposed, which has several advantages: it is faster, its accuracy can be quickly estimated, and tradeoffs between runtime and optimality can easily be made. Furthermore, the MLP model also provides a way to estimate a lower bound on circuit leakage current. The proposed methods are used to generate an extensive set of experimental results on leakage reduction. It is shown that average leakage currents are usually 1.25 times the minimum, confirming the effectiveness of IVC. The heuristic MLP approach is shown to be approximately 13.6 times faster than the exact ILP method, whereas finding input vectors whose power consumption is only a few percent above the optimum. In addition, the lower bound estimated by the MLP model is also within a few percent of the optimal value View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the areas of computer-aided design of integrated circuits and systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu