By Topic

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Issue 10 • Date Oct. 2006

Filter Results

Displaying Results 1 - 18 of 18
  • Table of contents

    Publication Year: 2006, Page(s): c1
    Request permission for commercial reuse | PDF file iconPDF (38 KB)
    Freely Available from IEEE
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

    Publication Year: 2006, Page(s): c2
    Request permission for commercial reuse | PDF file iconPDF (35 KB)
    Freely Available from IEEE
  • Efficient Synchronization for Embedded On-Chip Multiprocessors

    Publication Year: 2006, Page(s):1049 - 1062
    Cited by:  Papers (15)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1423 KB) | HTML iconHTML

    This paper investigates optimized synchronization techniques for shared memory on-chip multiprocessors (CMPs) based on network-on-chip (NoC) and targeted at future mobile systems. The proposed solution is based on the idea of locally performing synchronization operations requiring continuous polling of a shared variable, thus, featuring large contentions (e.g., spin locks and barriers). A hardware... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • High Rate Data Synchronization in GALS SoCs

    Publication Year: 2006, Page(s):1063 - 1074
    Cited by:  Papers (31)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1275 KB) | HTML iconHTML

    Globally asynchronous, locally synchronous (GALS) systems-on-chip (SoCs) may be prone to synchronization failures if the delay of their locally-generated clock tree is not considered. This paper presents an in-depth analysis of the problem and proposes a novel solution. The problem is analyzed considering the magnitude of clock tree delays, the cycle times of the GALS module, and the complexity of... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Runtime Leakage Minimization Through Probability-Aware Optimization

    Publication Year: 2006, Page(s):1075 - 1088
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1201 KB) | HTML iconHTML

    Runtime leakage current, defined as circuit leakage during normal operation (i.e., nonstandby mode), has become a major concern in very advanced technologies along with traditional standby mode leakage. In this paper, we propose a new leakage reduction method that specifically targets runtime leakage current. We first observe that the state probabilities of nodes in a circuit tend to be skewed, me... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Wake-Up Logic Optimizations Through Selective Match and Wakeup Range Limitation

    Publication Year: 2006, Page(s):1089 - 1102
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1304 KB) | HTML iconHTML

    This paper presents two effective wakeup designs that improve the speed, power, area, and scalability without instructions per cycle (IPC) loss for dynamic instruction schedulers. First, a wakeup design is proposed to aim at reducing the power consumption and wakeup latency. This design removes the read of the destination tags from the wakeup path by matching the source tags directly with the gran... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • HVS-Aware Dynamic Backlight Scaling in TFT-LCDs

    Publication Year: 2006, Page(s):1103 - 1116
    Cited by:  Papers (31)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2334 KB) | HTML iconHTML

    Liquid crystal displays (LCDs) have appeared in applications ranging from medical equipment to automobiles, gas pumps, laptops, and handheld portable computers. These display components present a cascaded energy attenuator to the battery of the handheld device which is responsible for about half of the energy drain at maximum display intensity. As such, the display components become the main focus... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Quasi-Static Assignment of Voltages and Optional Cycles in Imprecise-Computation Systems With Energy Considerations

    Publication Year: 2006, Page(s):1117 - 1129
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (800 KB) | HTML iconHTML

    For some realtime systems, it is possible to tradeoff precision for timeliness. For such systems, typically considered under the imprecise computation model, a function assigns reward to the application depending on the amount of computation allotted to it. Also, these systems often have stringent energy constraints since many such applications run on battery powered devices. We address in this pa... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Timing-Aware Probabilistic Model for Single-Event-Upset Analysis

    Publication Year: 2006, Page(s):1130 - 1139
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (710 KB) | HTML iconHTML

    With device size shrinking and fast rising frequency ranges, the effect of cosmic radiations and alpha particles known as single-event upset (SEU) and single-event transients (SET), is a growing concern in logic circuits. Accurate understanding and estimation of SEU sensitivities of individual nodes is necessary to achieve better soft error hardening techniques at logic level design abstraction. W... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Statistical Timing Yield Optimization by Gate Sizing

    Publication Year: 2006, Page(s):1140 - 1146
    Cited by:  Papers (13)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (661 KB) | HTML iconHTML

    In this paper, we propose a statistical gate sizing approach to maximize the timing yield of a given circuit, under area constraints. Our approach involves statistical gate delay modeling, statistical static timing analysis, and gate sizing. Experiments performed in an industrial framework on combinational International Symposium on Circuits and Systems (ISCAS'85) and Microelectronics Center of No... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Highly-Parallel Decoding Architectures for Convolutional Turbo Codes

    Publication Year: 2006, Page(s):1147 - 1151
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (192 KB) | HTML iconHTML

    Highly parallel decoders for convolutional turbo codes have been studied by proposing two parallel decoding architectures and a design approach of parallel interleavers. To solve the memory conflict problem of extrinsic information in a parallel decoder, a block-like approach in which data is written row-by-row and read diagonal-wise is proposed for designing collision-free parallel interleavers. ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • DTMOS Technique for Low-Voltage Analog Circuits

    Publication Year: 2006, Page(s):1151 - 1156
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (499 KB) | HTML iconHTML

    In this paper, the application of dynamic threshold MOS (DTMOS) technique for low-voltage analog circuits is explored. The body terminal of PMOS transistors in bulk CMOS technology can be used as the forth terminal to enhance the performance of low-voltage analog circuits. To show the effectiveness of this technique, we have designed a continuous time common mode feedback (CMFB) circuit for a sub ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Reduced Complexity Interpolation Architecture for Soft-Decision Reed–Solomon Decoding

    Publication Year: 2006, Page(s):1156 - 1161
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (297 KB) | HTML iconHTML

    Reed-Solomon (RS) codes are one of the most widely utilized block error-correcting codes in modern communication and computer systems. Compared to hard-decision decoding, soft-decision decoding offers considerably higher error-correcting capability. The Koetter-Vardy (KV) soft-decision decoding algorithm can achieve substantial coding gain, while maintaining a complexity polynomial with respect to... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Leading the field since 1884 [advertisement]

    Publication Year: 2006, Page(s): 1162
    Request permission for commercial reuse | PDF file iconPDF (218 KB)
    Freely Available from IEEE
  • Quality without compromise [advertisement]

    Publication Year: 2006, Page(s): 1163
    Request permission for commercial reuse | PDF file iconPDF (319 KB)
    Freely Available from IEEE
  • IEEE order form for reprints

    Publication Year: 2006, Page(s): 1164
    Request permission for commercial reuse | PDF file iconPDF (354 KB)
    Freely Available from IEEE
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information

    Publication Year: 2006, Page(s): c3
    Request permission for commercial reuse | PDF file iconPDF (25 KB)
    Freely Available from IEEE
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems Information for authors

    Publication Year: 2006, Page(s): c4
    Request permission for commercial reuse | PDF file iconPDF (29 KB)
    Freely Available from IEEE

Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu