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IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Issue 9 • Date Sept. 2006

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Displaying Results 1 - 17 of 17
  • Table of contents

    Publication Year: 2006, Page(s): C1
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

    Publication Year: 2006, Page(s): C2
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  • A Lossless Data Compression and Decompression Algorithm and Its Hardware Architecture

    Publication Year: 2006, Page(s):925 - 936
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1686 KB) | HTML iconHTML

    In this paper, we propose a new two-stage hardware architecture that combines the features of both parallel dictionary LZW (PDLZW) and an approximated adaptive Huffman (AH) algorithms. In this architecture, an ordered list instead of the tree-based structure is used in the AH algorithm for speeding up the compression data rate. The resulting architecture shows that it not only outperforms the AH a... View full abstract»

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  • High-Speed Interpolation Architecture for Soft-Decision Decoding of Reed–Solomon Codes

    Publication Year: 2006, Page(s):937 - 950
    Cited by:  Papers (24)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (664 KB) | HTML iconHTML

    Algebraic soft-decision decoding of Reed-Solomon (RS) codes delivers promising coding gains over conventional hard-decision decoding. The most computationally demanding step in soft-decision decoding of RS codes is bivariate polynomial interpolation. In this paper, we present a hybrid data format-based interpolation architecture that is well suited for high-speed implementation of the soft-decisio... View full abstract»

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  • Fast Decimal Floating-Point Division

    Publication Year: 2006, Page(s):951 - 961
    Cited by:  Papers (28)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (589 KB) | HTML iconHTML

    A new implementation for decimal floating-point (DFP) division is introduced. The algorithm is based on high-radix SRT division The SRT division algorithm is named after D. Sweeney, J. E. Robertson, and T. D. Tocher. with the recurrence in a new decimal signed-digit format. Quotient digits are selected using comparison multiples, where the magnitude of the quotient digit is calculated by comparing... View full abstract»

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  • An Efficient Digital VLSI Implementation of Gaussian Mixture Models-Based Classifier

    Publication Year: 2006, Page(s):962 - 974
    Cited by:  Papers (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (929 KB) | HTML iconHTML

    Gaussian mixture models (GMM)-based classifiers have shown increased attention in many pattern recognition applications. Improved performances have been demonstrated in many applications, but using such classifiers can require large storage and complex processing units due to exponential calculations and a large number of coefficients involved. This poses a serious problem for portable real-time p... View full abstract»

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  • An Asynchronous Low-Power High-Performance Sequential Decoder Implemented With QDI Templates

    Publication Year: 2006, Page(s):975 - 985
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1489 KB) | HTML iconHTML

    This paper presents the design of a channel-based asynchronous sequential decoder implemented with quasi-delay-insensitive templates. The Powermill simulation results in TSMC 0.25-CMOS technology show that the circuit runs at 430 MHz and consumes 32 mW. Techniques to effectively partition and implement the top level design, the implementation of fast shift registers, memories, and various other st... View full abstract»

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  • Architecture and Compiler Optimizations for Data Bandwidth Improvement in Configurable Processors

    Publication Year: 2006, Page(s):986 - 997
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1982 KB) | HTML iconHTML

    Many commercially available embedded processors are capable of extending their base instruction set for a specific domain of applications. While steady progress has been made in the tools and methodologies of automatic instruction set extension for configurable processors, the limited data bandwidth available in the core processor (e.g., the number of simultaneous accesses to the register file) be... View full abstract»

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  • Via-Configurable Routing Architectures and Fast Design Mappability Estimation for Regular Fabrics

    Publication Year: 2006, Page(s):998 - 1009
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2744 KB) | HTML iconHTML

    In this paper, we describe a new via-configurable routing architecture which shows a much better throughput and performance than the previous structures. We demonstrate how to construct a single-via-mask fabric to reduce the mask cost further, and we analyze the penalties which it incurs. To solve the routability problem commonly existing in fabric-based designs, an efficient white-space allocatio... View full abstract»

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  • Mapping Data-Parallel Tasks Onto Partially Reconfigurable Hybrid Processor Architectures

    Publication Year: 2006, Page(s):1010 - 1023
    Cited by:  Papers (11)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1155 KB) | HTML iconHTML

    Reconfigurable hybrid processor systems provide a flexible platform for mapping data-parallel applications, while providing considerable speedup over software implementations. However, the overhead for reconfiguration presents a significant deterrent in mapping applications onto reconfigurable hardware. Partial runtime reconfiguration is one approach to reduce the reconfiguration overhead. In this... View full abstract»

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  • Application-Dependent Testing of FPGAs

    Publication Year: 2006, Page(s):1024 - 1033
    Cited by:  Papers (27)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (678 KB) | HTML iconHTML

    Testing techniques for interconnect and logic resources of an arbitrary design implemented into a field-programmable gate array (FPGA) are presented. The target fault list includes all stuck-at, open, and pair-wise bridging faults in the mapped design. For interconnect testing, only the configuration of the used logic blocks is changed, and the structure of the design remains unchanged. For logic ... View full abstract»

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  • Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis

    Publication Year: 2006, Page(s):1034 - 1039
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (482 KB) | HTML iconHTML

    Power consumption in datapath modules due to redundant switching is an important design concern for high-performance applications. Operand isolation schemes that reduce this redundant switching incur considerable overhead in terms of delay, power, and area. This paper presents novel operand isolation techniques based on supply gating that reduce overheads associated with isolating circuitry. The p... View full abstract»

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  • Hybrid-Scheduling for Reduced Energy Consumption in High-Performance Processors

    Publication Year: 2006, Page(s):1039 - 1043
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (224 KB) | HTML iconHTML

    This paper develops a technique that uniquely combines the advantages of compile-time static scheduling and hardware dynamic scheduling to reduce energy consumption in dynamically scheduled processors. In this hybrid-scheduling paradigm, regions of the application containing large amounts of parallelism visible at compile-time bypass the dynamic scheduling hardware and execute in a low-power stati... View full abstract»

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  • Minimal Energy Asynchronous Dynamic Adders

    Publication Year: 2006, Page(s):1043 - 1047
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (306 KB) | HTML iconHTML

    In battery-operated portable or implantable digital devices, where battery life needs to be maximized, it is necessary to minimize not only power consumption but also energy dissipation. Typical energy optimization measures include voltage reduction and operating at the slowest possible speed. We employ additional methods, including hybrid asynchronous dynamic design to enable operating over a wid... View full abstract»

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    Publication Year: 2006, Page(s): 1048
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information

    Publication Year: 2006, Page(s): C3
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems Information for authors

    Publication Year: 2006, Page(s): C4
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Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

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Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu