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Circuits and Systems I: Regular Papers, IEEE Transactions on

Issue 10 • Date Oct. 2006

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Displaying Results 1 - 25 of 35
  • Table of contents

    Page(s): c1 - c4
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    Freely Available from IEEE
  • IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

    Page(s): c2
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    Freely Available from IEEE
  • Architecture and Implementation of a Low-Power LVDS Output Buffer for High-Speed Applications

    Page(s): 2101 - 2108
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1743 KB) |  | HTML iconHTML  

    This paper presents a new detailed analysis of low-voltage differential signaling (LVDS) output buffers that are intended for use in high-speed integrated circuits. Three theoretically possible architectures of a LVDS output driver are discussed in rigorous detail, resulting in the recognition of the most power-conserving circuit configuration. An innovative realization of this identified low-power architecture is presented in this paper along with computer simulation results and test lab measurement data. The novel LVDS driver is designed using a unique hetero-junction bipolar transistor structure. Computer simulation results show total current consumption of 6.3 mA for the bipolar driver at a 1-GHz clock frequency while operating from a positive supply voltage between 1.7 and 3.3 V, as well as demonstrate full stage compliance with all the requirements of the IEEE 1596.3-1996 standard. The presented version of the buffer was utilized in a multiplexer/demultiplexer chip set that was fabricated in a modern 50-GHz-fT SiGe technology. Test results of the LVDS output buffer taken from five different chip samples reveal high-quality output eyes with more than 0.99 UI opening and close matching between the measured parameters and simulation results View full abstract»

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  • An A/D Converter for Multimode Wireless Receivers, Based on the Cascade of a Double-Sampling \Sigma \Delta Modulator and a Flash Converter

    Page(s): 2109 - 2124
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    This work proposes an architecture for an analog-to-digital converter intended for a multimode wireless receiver. The architecture is based on the cascade of a single-bit 2-1 sigma-delta modulator and a 4-bit flash converter. Furthermore such an architecture is mapped in a modular implementation, which allows to easily reconfigure modulator order, oversampling ratio and equivalent number of bits of the internal quantizer. As a consequence, the proposed converter can fulfil the requirement of a wide range of standards: Global System for Mobile Communications (GSM), Bluetooth, universal mobile telecommunications system (UMTS), and wireless local area network (WLAN)a. The paper discusses extensively the effects of circuit nonidealities on the converter performance, in order to single out the most suited setup for the programmable parameters and to demonstrate the practical feasibility of the proposed system. The converter figures of merit have been quantified by means of transistor-level and behavioral simulations: the achieved dynamic range is 85, 72, 62, and 59 dB for GSM, Bluetooth, UMTS, and WLANa, respectively. The corresponding power consumption is 4.6, 5.5, 7.4, and 18.9 mW View full abstract»

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  • A 1.2- V 30.4-dBm OIP3 Reconfigurable Analog Baseband Channel for UMTS/WLAN Transmitters

    Page(s): 2125 - 2131
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    This paper presents a reconfigurable universal mobile telecommunication systems [(UMTS) and wireless local area network (WLAN) mode)] analog baseband transmitter channel composed of a current steering digital-analog converter (DAC), a transimpedance stage, and a low-pass reconstruction filter. The device operates from a single 1.2-V supply voltage while guaranteeing the high-linearity UMTS/WLAN standard requirements. It can be digitally programmed to process WLAN 802.11a/b/g and UMTS signals, by adjusting the DAC conversion frequency and the low-pass filter cutoff frequency. For the WLAN mode, the DAC operating frequency and the filter bandwidth are set to 100 and 11 MHz, respectively, while for the UMTS mode, they are equal to 50 and 2.11 MHz. The device is realized in a 1.2-V 0.13-mum standard CMOS technology. The die area occupation, equal to 0.9mm2, has been minimized by optimizing the component sharing for the two operation modes. The proposed circuit achieves a 30.4 dBm third-order output referred intermodulation intercept point (OIP3) for the WLAN mode, and a 31.5 dBm-OIP3 when configured for the UMTS mode, while the spurious-free dynamic range is 58 dB for WLAN mode, and 60 dB for UMTS mode. The power consumption is optimized according to the operation mode and is 19.44 mW in WLAN mode and 16.8 mW in UMTS mode View full abstract»

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  • A New Multistage Noise-Shaping Architecture

    Page(s): 2132 - 2144
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    This paper presents a new architecture for high dynamic range, low oversampling ratio (OSR) noise-shaped digital-to-analog converters (DACs). The instantaneous noise feedforward architecture is a multistage structure in which the instantaneous noise and gain/phase distortion in the first stage are cancelled by passing them through another converter and then subtracting them at the output after analog attenuation. The signal-to-noise-and-distortion ratio (SNDR) of a device using this architecture scales as the product of the first noise shaper's SNDR and the ratiometric precision of the attenuator technology. This new architecture was implemented by driving the bits of an existing DAC (with binary weighting) using specially generated digital signals. One set of experimental measurements demonstrates a spurious-free dynamic range (SFDR) performance of 83 dBc in a 125-MHz bandwidth centered at 325 MHz while using an OSR of only 4. A second set of experimental measurements produces an SFDR performance of 70 dBc in a 125-MHz bandwidth centered slightly above 1.3 GHz with an OSR of 16 View full abstract»

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  • Mixed-Domain Systems and Signal Processing Based on Input Decomposition

    Page(s): 2145 - 2156
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    Using input decomposition as a starting point, a variety of new types of systems and signal processors, which mix together domains traditionally kept separate, are derived, and their properties are examined. In one of these systems, digital signals are processed in continuous time, thus avoiding sampling and consequent aliasing, while maintaining the advantages of digital implementations in terms of programmability and noise immunity. In another approach, digital bit waveforms are processed directly by conventional analog filters. In a third approach, a nonlinear input decomposition results in systems in which signals are processed with a compressed dynamic range; this is done in a way that avoids output transients that characterize other approaches to compression, and also avoids the need for precise nonlinearity control. Several other possibilities are discussed. In all cases, the resulting systems can be input-output linear View full abstract»

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  • VCO Design With On-Chip Calibration System

    Page(s): 2157 - 2166
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    This paper presents a low-supply voltage integrated CMOS voltage-controlled oscillator (VCO) with an on-chip digital VCO calibration control system. The VCO utilizes various state-of-the-art design methods to achieve low phase noise. The calibration system includes a novel high-speed digital divide by two circuit and a counter running on 1-GHz input to enable on-chip frequency measurement. An arithmetic unit and algorithms to perform the calibration are implemented using on-chip logic. Two different types of calibration methods have been implemented and measured in order to compare the proposed VCO gain optimization method with more conventional type of VCO calibration. The measurements show that the VCO design has phase noise from -120.5 dBc/Hz to -118.7 dBc/Hz @ 400-kHz offset, measured over the frequency range from 1.67 to 1.93 GHz. The proposed VCO gain optimization method is capable of reducing the KVCO peak-to-peak variation of the presented VCO design from 54.4% to 29.8% in DCS1800 and PCS1900 GSM transmission bands when compared to the conventional type of calibration method View full abstract»

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  • A Simple Way for Substrate Noise Modeling in Mixed-Signal ICs

    Page(s): 2167 - 2177
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    Here is a complete methodology of substrate noise modeling. The aim of this study is to predict the perturbations induced by digital commutations flowing through the substrate to reach sensitive analog blocks. Till now, the studies have only taking into account the parasitic elements of the bonding wires. This work consists of each part of a mixed-signal design that induces power-and-ground bounces: the printed circuit board, the package, the bonding wires, the input-output ring, the on-chip power-supply distribution, and the digital core of the chip. A standard approach, called integrated circuit (IC) emission model, is used to create the substrate simulation model. By adding some elements to this power-supply model, we can simulate the transient substrate voltage induced by the digital part of a mixed-signal IC. A test chip has been realized in a 0.35-mum BiCMOS process to validate this substrate coupling model. Power-supply network, chip activity and substrate propagation of this circuit are obtained by using classical computer-aided design tools. Some Spice simulations of the modeled test chip, running in many different configurations, are shown. Comparisons between measurements and simulations are done and lead to the conception of an optimized version of the same circuit that induces less parasitic substrate voltages View full abstract»

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  • Adaptive Multiple-Resolution CMOS Active Pixel Sensor

    Page(s): 2178 - 2186
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    A smart image sensor with adaptive multiple resolution ability is presented. This sensor is based on the quadtree decomposition algorithm, which decomposes an image into square homogeneous regions. After the image is segmented, only the value of the block and its size are stored or transmitted. On-chip implementation can solve the information bottleneck problem by reducing the amount of data for transmission. Good compression results can be achieved for scenes with predominant and homogeneous backgrounds. The algorithm is implemented on chip in a mixed-signal column parallel architecture in 0.35-mum 4M2P n-well TSMC CMOS technology available through MOSIS. Typical power dissipation for the test chip with 32times32 pixels is 70 mW at VDD=3.3 V View full abstract»

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  • Design on Power-Rail ESD Clamp Circuit for 3.3-V I/O Interface by Using Only 1-V/2.5-V Low-Voltage Devices in a 130-nm CMOS Process

    Page(s): 2187 - 2193
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    A new power-rail electrostatic discharge (ESD) clamp circuit for application in 3.3-V mixed-voltage input-output (I/O) interface is proposed and verified in a 130-nm 1-V/2.5-V CMOS process. The devices in this power-rail ESD clamp circuit are all 1-V or 2.5-V low-voltage nMOS/pMOS devices, which are specially designed without suffering the gate-oxide reliability issue under 3.3-V I/O interface applications. A special ESD detection circuit realized with the low-voltage devices is designed and added in the power-rail ESD clamp circuit to improve ESD robustness of ESD clamp devices by substrate-triggered technique. The experimental results verified in a 130-nm CMOS process have proven the excellent effectiveness of this new proposed power-rail ESD clamp circuit View full abstract»

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  • A 16-Bit Barrel-Shifter Implemented in Data-Driven Dynamic Logic ( D ^3 L )

    Page(s): 2194 - 2202
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    Data-driven dynamic logic (D3L) uses local data instead of a global clock to maintain correct precharge and evaluation phases. Eliminating the clock from dynamic gates yields less power consumption and faster gate operation. Two 16-bit barrel shifters are implemented in a 5-V 0.6-mum CMOS technology: one in normal Domino logic and the other in our proposed D3L. Separate power leads are used on the chip to measure power consumption of separate sections. Post-layout simulations show that, depending on input patterns, a D3L shifter consumes 8% to 62% less power and is 29% faster than the Domino circuit. In addition, it provides an additional 9% area advantage over its Domino rival. Experimental measurements confirm post-layout simulation results, and prove the feasibility of the proposed logic View full abstract»

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  • Realization of Boolean Functions via CNN: Mathematical Theory, LSBF and Template Design

    Page(s): 2203 - 2213
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (544 KB) |  | HTML iconHTML  

    As a paradigm for nonlinear spatial-temporal processing, cellular nonlinear networks (CNN) are biologically inspired systems where computation emerges from a collection of simple locally coupled nonlinear cells. Our investigation is an exploration of an important and difficult aspect of implementing arbitrary Boolean functions by using CNN. A typical class of basic key Boolean functions is the class of linearly separable ones. In this paper, we focus on establishing a complete set of mathematical theories for the linearly separable Boolean functions (LSBF) that are identical to a class of uncoupled CNN. First, we obtain an essential relationship between the template and the offset levels as well as the basis of the binary input vector set in the uncoupled CNN. More precisely, we construct a neat binary input-output truth table and some interesting properties of the offset levels of the uncoupled CNN, and develop a practical design formula for the class of CNN template. Especially, we found a criterion for LSBF, which depends only on symbolic relations between a Boolean function's outputs. Furthermore, we develop a method for representing any linearly nonseparable Boolean function into a logic operation of a sequence of linearly separable ones for a small number of inputs View full abstract»

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  • Admittance Matrix Models for the Nullor Using Limit Variables and Their Application to Circuit Design

    Page(s): 2214 - 2223
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    A framework for symbolic analysis and synthesis of linear active circuits has previously been proposed which is based on the use of admittance matrices and infinity-variables. The notation has the important advantage that it can describe both ideal circuit elements, for which an infinite limit is implied, and nonideal circuit elements for which matrix elements are considered finite. The nullor is a very important circuit element because it can represent the ideal operational amplifier and the ideal transistor. For the nonideal case, the use of finite matrix elements implies that the operational amplifier and transistor are both modelled as a voltage-controlled current source, which is fine if the transistor is a field effect transistor or if the operational amplifier is of the transconductance type, but not otherwise. The purpose of this paper is to apply the infin-variable framework in order to derive alternative models for the nullor that can be used to model voltage, current and transresistance operational amplifiers and bipolar junction transistors. We also show that the infin-variable description of an ideal transistor can include a factor to represent transistor geometry View full abstract»

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  • Fuzzy Impulsive Control of High-Order Interpolative Low-Pass Sigma–Delta Modulators

    Page(s): 2224 - 2233
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    In this paper, a fuzzy impulsive control strategy is proposed. The state vectors that the impulsive controller resets to are determined so that the state vectors of interpolative low-pass sigma-delta modulators (SDMs) are bounded within any arbitrary nonempty region no matter what the input step size, the initial condition and the filter parameters are, the occurrence of limit cycle behaviors and the effect of audio clicks are minimized, as well as the state vectors are close to the invariant set if it exists. To work on this problem, first, the local stability criterion and the condition for the occurrence of limit cycle behaviors are derived. Second, based on the derived conditions, as well as a practical consideration based on the boundedness of the state variables and a heuristic measure on the strength of audio clicks, fuzzy membership functions and a fuzzy impulsive control law are formulated. The controlled state vectors are then determined by solving the fuzzy impulsive control law. One of the advantages of the fuzzy impulsive control strategy over the existing linear control strategies is the robustness to the input signal, the initial condition and the filter parameters, and that over the existing nonlinear control strategy are the efficiency and the effectiveness in terms of lower frequency of applying the control force and higher signal-to-noise ratio (SNR) performance View full abstract»

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  • Mitigating ISI Through Self-Calibrating Continuous-Time Equalization

    Page(s): 2234 - 2245
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    A method for designing self-calibrating continuous-time equalizers is proposed. Two distinct error terms, generated from the channel pulse response, may be used to adaptively calibrate the equalizer, resulting in a significant reduction of intersymbol interference (ISI). Both error terms are based on the minimization of accumulating ISI versus total ISI. By limiting the change in ISI from bit to bit, reasonable voltage and timing margins are achieved. Matlab simulations show the clear opening of 10-Gb/s data eyes across 6 in and 20 in of FR4, as well as the clear opening of a 20-Gb/s data eye across 6 in of the same medium View full abstract»

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  • Linear Controllers for the Stabilization of Unknown Steady States of Chaotic Systems

    Page(s): 2246 - 2254
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    The problem of stabilization of unknown steady states of chaotic systems by means of linear controllers is studied. A complete solution of the problem is given for the case of state feedback stabilization. For the case of output feedback stabilization, some partial results are given. The paper shows that the control theoretic concepts of controllability, stabilizability and root-locus are instrumental in the solution of the problem. All results are illustrated by means of the stabilization of unknown steady states of a controlled Lorenz system View full abstract»

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  • Synthesis of Reduced Equivalent Circuits for Transmission Lines

    Page(s): 2255 - 2264
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    This paper presents a method for generating lumped models for symmetrical transmission-line two-ports. These models consist of an ideal transformer and frequency-domain approximations for two physical driving-point impedances. The lumped element values are obtained directly from the distributed parameters or propagation constant and characteristic impedance. The method is applied to dispersive transmission lines, skin effect and waveguides. It is shown that the equivalent circuit is superior in accuracy and number of elements compared to spatial discretizations like ladder approximation View full abstract»

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  • Robust Stability and Robust Periodicity of Delayed Recurrent Neural Networks With Noise Disturbance

    Page(s): 2265 - 2273
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (424 KB) |  | HTML iconHTML  

    Neural networks suffer from the natural intra- and inter-cellular noise perturbations and environmental fluctuations. Such noises will undoubtedly affect the dynamics of the neural networks both quantitatively and qualitatively. In this paper, we study the effects of noise perturbations on the stability and periodicity of delayed recurrent neural networks. We first derive the mean-square stability conditions for stochastic delayed recurrent neural networks without and with parametric uncertainties, respectively. After that, we study the stochastic periodicity (stability) with disturbance attenuation of delayed recurrent neural networks. The analysis are all based on the Lyapunov-Krasovskii functional approach, and the conditions are all expressed in terms of linear matrix inequalities, which can be easily solved by using the effective convex optimization techniques. Several numerical examples are also given to demonstrate the correctness and effectiveness of the theoretical results View full abstract»

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  • Analysis and Design for a Novel Single-Stage High Power Factor Correction Diagonal Half-Bridge Forward AC–DC Converter

    Page(s): 2274 - 2286
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    By means of components placement, the buck-boost and diagonal half-bridge forward converters are combined to create a novel single-stage high power factor correction (HPFC) diagonal half-bridge forward converter. When both the PFC cell and dc-dc cell operate in DCM, the proposed converter can achieve HPFC and lower voltage stress of the bulk capacitor. The circuit analysis of the proposed converter operating in DCM+DCM mode is presented. In order to design controllers for the output voltage regulation, the ac small-signal model of the proposed converter is derived by the averaging method. Based on the derived model, the proportional integral (PI) controller and minor-loop controller are then designed. The simulation and experimental results show that the proposed converter with the minor-loop controller has faster output voltage regulation than that with the PI controller despite the variations of line voltage and load. Finally, a 100-W prototype of the proposed ac-dc converter is implemented and the theoretical result is experimentally verified View full abstract»

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  • Simultaneous Blind Separation of Instantaneous Mixtures With Arbitrary Rank

    Page(s): 2287 - 2298
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    This paper presents a gradient-based method for simultaneous blind separation of arbitrarily linearly mixed source signals. We consider the regular case (i.e., the mixing matrix has full column rank) as well as the ill-conditioned case (i.e., the mixing matrix does not have full column rank). We provide one necessary and sufficient condition for the identifiability of simultaneous blind separation. According to our identifiability condition and the existing general identifiability condition, all source signals are separated into two categories: separable single sources and inseparable mixtures of several single sources. A sufficient condition is also derived for the existence of optimal partition of the mixing matrix which leads to a unique maximum set of separations. One sufficient condition is proved to show that each maximum partition of the mixing matrix corresponds to a unique class of separated signals and as a result we can determine the number of maximum partitions from the classes of outputs under different separation matrices. For sub-Gaussian or super-Gaussian source signals, a cost function based on fourth-order cumulants is introduced to simultaneously separate all separable single sources and all inseparable mixtures. By minimizing the cost function, a gradient-based method is developed. Finally, simulation results show the effectiveness of the present method View full abstract»

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  • Clock Synchronization Errors in Circuits: Models, Stability and Fault Detection

    Page(s): 2299 - 2305
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    This paper models and analyzes the effect of multiple sub-systems that are driven by the same clock signal with active clock edges reaching subsystems at different time instants. This type of problem appears in high speed circuits and systems where the clock signal propagation delays differ significantly and the global system properties of the ideally synchronously switching system are changed. Fault detection and identification methods for this type of system are provided, by using a state-space approach to asynchronously switching systems View full abstract»

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  • On Synchronization Errors in Networked Feedback Systems

    Page(s): 2306 - 2317
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    This paper addresses the problem of synchronization errors and their effects on feedback loops that are closed over communication networks. It is assumed that the feedback loop consists of two discrete-time systems, the clock frequency ratio of which has a special rational form, and is close to one. A Toeplitz matrix approach is taken to model the input/output relationship of the arising feedback systems. Based on this representation, the effect of synchronization errors on stability of the feedback systems is analyzed. It is shown that stability of the synchronized feedback loop can not guarantee stability of the loop in the presence of synchronization errors. Necessary and sufficient stability conditions are derived View full abstract»

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  • Recurrence Plot-Based Approach to the Analysis of IP-Network Traffic in Terms of Assessing Nonstationary Transitions Over Time

    Page(s): 2318 - 2326
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    This paper presents a recurrence plot scheme approach to the analysis of nonstationary transition patterns of IP-network traffic. In performing a quantitative assessment of dynamical transition patterns of IP-network traffic, we used the values of determinism (DET) defined by the recurrence quantification analysis (RQA). Also, in evaluating fractal-related properties of IP-network traffic, we employed the detrended fluctuation analysis (DFA), which is applicable to the analysis of long-range dependence (LRD) in nonstationary time-series signals. Furthermore, to obtain a comprehensive view of network traffic conditions, we used a self-organizing map, which provides a way to map high-dimensional data onto a low-dimensional domain. When applying this method to traffic analysis, we performed two kinds of traffic measurement in Tokyo, Japan, and derived values of DET and the LRD-based scaling parameter alpha of IP-network traffic. Then, we found that the characteristic with respect to DET and self-similarity seen in the measured traffic fluctuated over time, with different time variation patterns for two measurements. In training the self-organizing map, we used three parameters: average throughput, variation ratio of DET, and alpha value. As a result, we visually confirmed that the traffic data could be projected onto the map in accordance with traffic properties, resulting in a combined depiction of the effects of the DET and network utilization rates on the time-variations of LRD View full abstract»

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  • Vector Autoregressive Model-Order Selection From Finite Samples Using Kullback's Symmetric Divergence

    Page(s): 2327 - 2335
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (375 KB) |  | HTML iconHTML  

    In this paper, a new small-sample model selection criterion for vector autoregressive (VAR) models is developed. The proposed criterion is named Kullback information criterion (KICvc), where the notation vc stands for vector correction, and it can be considered as an extension of the KIC, for VAR models. KICvc adjusts KIC to be an unbiased estimator for the variant of the Kullback symmetric divergence, assuming that the true model is correctly specified or overfitted. Furthermore, KICvc provides better VAR model-order choices than KIC in small samples. Simulation results show that the proposed criterion selects the model order more accurately than other asymptotically efficient methods when applied to VAR model selection in small samples. As a result, KICvc serves as an effective tool for selecting a VAR model of appropriate order. A theoretical justification of the proposed criterion is presented View full abstract»

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Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

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Meet Our Editors

Editor-in-Chief
Shanthi Pavan
Indian Institute of Technology, Madras