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Computer

Issue 4 • Date April 1992

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Displaying Results 1 - 8 of 8
  • Task-flow architecture for WSI parallel processing

    Page(s): 10 - 18
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1747 KB)  

    The basics of task-flow architecture and the simulated wafer-scale implementation of flowing tasks (SWIFT), a register-transfer simulator that investigates the behavior of task-flow programs, are discussed. SWIFT simulates a ring of cells with two pipeline stages between successive cells. Each cell contains an arithmetic logic unit (ALU), a receive queue for holding incoming transmission packets, and a memory for storing memory packets (MPs). The chain wafer-scale integration (WSI) architecture that allows linear arrays to be configured from the working cells on a partially good wafer is applied to task-flow-machine implementations. Results from a limited Monte Carlo simulation run to predict yields for a 164-cell wafer configured using the chain WSI technique are presented. Results of a simulated sparse matrix-vector multiplication application of the task-flow architecture are also presented.<> View full abstract»

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  • A design and yield evaluation technique for wafer-scale memory

    Page(s): 19 - 27
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    Wafer-scale memory provides greater yet cheaper storage volume than conventional memory systems using discrete chips. A simulator using a Monte Carlo technique to evaluate the defect tolerance scheme for a wafer-scale memory and predict the harvested capacity of the wafer memory is described. The design of a wafer-scale random-access memory that uses switching-register network logic is presented. A simulator that selects the optimal defect tolerance scheme for the wafer-scale memory is discussed.<> View full abstract»

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  • Configuring a wafer-scale two-dimensional array of single-bit processors

    Page(s): 29 - 39
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    An overview of the ELSA (European large SIMD array) project, which uses a two-level strategy to achieve defect tolerance for wafer-scale architectures implemented in silicon, is presented. The target architecture is a 2-D array of processing elements for low-level image processing. An array is divided into subarrays called chips. At the chip level, defect tolerance is proved by an extra column of PEs (processing element) and bypassing techniques. At the wafer level, a double-rail connection network is used to construct a target array of defect-free chips that is as large and as fast as possible. Its main advantage is being independent of chip defects, as it is controlled from the I/O pads. An algorithm for constructing an optimized two-dimensional array on a wafer containing a given number of defect-free PEs and connections, a method to program the switches for the target architecture found by the algorithm, and software for programming the switches using laser cuts are discussed.<> View full abstract»

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  • Wafer-scale integration using restructurable VLSI

    Page(s): 41 - 47
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    Results from a restructurable very large scale integration (RVLSI) program show the viability of using a laser to restructure wafer-scale circuits for customization and defect avoidance. Wafer-scale circuits are built with a standard integrated circuit fabrication process when the diffused-link restructuring device is used. Nine wafer-scale systems that have been built using the RVLSI technique are described. It is shown that the laser interconnection process has high yield and provides the high reliability of monolithic circuitry. The technology is well suited to signal processing systems, which characteristically use many replications of a small number of circuits and often have modest interconnection requirements.<> View full abstract»

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  • Wafer-scale transducer arrays

    Page(s): 50 - 56
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    The production of wafer-scale transducer arrays using laser interconnection techniques and micromatching technology is discussed. The design of a wafer-scale thermal dynamic scene simulator that was implemented using the laser-linking redundancy technique is presented to illustrate typical design requirements. The simulator uses small arrays of thermal pixels and control circuitry in 3 mu m CMOS technology.<> View full abstract»

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  • Prospects for WSI: a manufacturing perspective

    Page(s): 58 - 65
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    A manufacturing cost model that describes the relationships among characteristics of modern manufacturing processes, investment costs to achieve these characteristics, and basic IC parameters, including both die size and minimum feature size, is used to explain major trends in the past 20 yr of microelectronics. Results from this model indicate that it is not possible to continue progress in microelectronics through minimizing feature size, that the drive toward larger dies will gain momentum and lead gradually toward wafer-scale integration (WSI), and that manufacturing costs will keep WSI from becoming practical in the immediate future. Active-substrate flip-chip multichip modules (MCMs) are presented as an alternative that may provide both the performance gain and cost efficiency required.<> View full abstract»

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  • Wafer-scale optimization using computational availability

    Page(s): 66 - 71
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    It is shown that, given the ability to restructure wafer-level designs, there are different ways to employ redundancy. Redundancy is evaluated by estimating system computational availability over a mission lifetime. This technique is illustrated using two wafer-scale integration (WSI) case studies. The first is a very-fine-grained programmable systolic data processor (PSDP) that contains 4- and 8-b paths, RAM, and control optimized for signal and data processing applications. The second, the Mosaic multicomputer architecture, is a less fine-grained homogeneous architecture in which each node contains a 16-b microprocessor and associated RAM and ROM. Potential benefits of implementing these parallel processing architectures in wafer scale are discussed.<> View full abstract»

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  • An architecture for WSI rapid prototyping

    Page(s): 71 - 75
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    Wafer-scale integration architecture for rapid prototyping (WARP), a generalized architecture for rapid prototyping, is discussed. The primary goal of rapid prototyping is to map one of several members of a class of algorithms using a single-wafer architecture. The wafer can be personalized for the algorithm by either soft or hard-restructuring. The WARP wafer consists of an array of two types of cells specifically defined for this architecture: the universal multiply-subtract-add (UMSA) cell and the universal nonlinear (UNL) cell. Reconfiguration of the algorithms in the presence of defects, a harvesting probability model and yield, and wafer-scale testing and test facilities are described.<> View full abstract»

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Computer, the flagship publication of the IEEE Computer Society, publishes highly acclaimed peer-reviewed articles written for and by professionals representing the full spectrum of computing technology from hardware to software and from current research to new applications.

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Editor-in-Chief
Ron Vetter
University of North Carolina
Wilmington