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Computer

Issue 4 • April 1992

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Displaying Results 1 - 8 of 8
  • Task-flow architecture for WSI parallel processing

    Publication Year: 1992, Page(s):10 - 18
    Cited by:  Papers (4)  |  Patents (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1747 KB)

    The basics of task-flow architecture and the simulated wafer-scale implementation of flowing tasks (SWIFT), a register-transfer simulator that investigates the behavior of task-flow programs, are discussed. SWIFT simulates a ring of cells with two pipeline stages between successive cells. Each cell contains an arithmetic logic unit (ALU), a receive queue for holding incoming transmission packets, ... View full abstract»

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  • A design and yield evaluation technique for wafer-scale memory

    Publication Year: 1992, Page(s):19 - 27
    Cited by:  Papers (4)  |  Patents (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1236 KB)

    Wafer-scale memory provides greater yet cheaper storage volume than conventional memory systems using discrete chips. A simulator using a Monte Carlo technique to evaluate the defect tolerance scheme for a wafer-scale memory and predict the harvested capacity of the wafer memory is described. The design of a wafer-scale random-access memory that uses switching-register network logic is presented. ... View full abstract»

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  • Configuring a wafer-scale two-dimensional array of single-bit processors

    Publication Year: 1992, Page(s):29 - 39
    Cited by:  Papers (13)  |  Patents (28)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2302 KB)

    An overview of the ELSA (European large SIMD array) project, which uses a two-level strategy to achieve defect tolerance for wafer-scale architectures implemented in silicon, is presented. The target architecture is a 2-D array of processing elements for low-level image processing. An array is divided into subarrays called chips. At the chip level, defect tolerance is proved by an extra column of ... View full abstract»

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  • Wafer-scale integration using restructurable VLSI

    Publication Year: 1992, Page(s):41 - 47
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2100 KB)

    Results from a restructurable very large scale integration (RVLSI) program show the viability of using a laser to restructure wafer-scale circuits for customization and defect avoidance. Wafer-scale circuits are built with a standard integrated circuit fabrication process when the diffused-link restructuring device is used. Nine wafer-scale systems that have been built using the RVLSI technique ar... View full abstract»

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  • Wafer-scale transducer arrays

    Publication Year: 1992, Page(s):50 - 56
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1123 KB)

    The production of wafer-scale transducer arrays using laser interconnection techniques and micromatching technology is discussed. The design of a wafer-scale thermal dynamic scene simulator that was implemented using the laser-linking redundancy technique is presented to illustrate typical design requirements. The simulator uses small arrays of thermal pixels and control circuitry in 3 mu m CMOS t... View full abstract»

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  • Prospects for WSI: a manufacturing perspective

    Publication Year: 1992, Page(s):58 - 65
    Cited by:  Papers (13)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (833 KB)

    A manufacturing cost model that describes the relationships among characteristics of modern manufacturing processes, investment costs to achieve these characteristics, and basic IC parameters, including both die size and minimum feature size, is used to explain major trends in the past 20 yr of microelectronics. Results from this model indicate that it is not possible to continue progress in micro... View full abstract»

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  • Wafer-scale optimization using computational availability

    Publication Year: 1992, Page(s):66 - 71
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1617 KB)

    It is shown that, given the ability to restructure wafer-level designs, there are different ways to employ redundancy. Redundancy is evaluated by estimating system computational availability over a mission lifetime. This technique is illustrated using two wafer-scale integration (WSI) case studies. The first is a very-fine-grained programmable systolic data processor (PSDP) that contains 4- and 8-... View full abstract»

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  • An architecture for WSI rapid prototyping

    Publication Year: 1992, Page(s):71 - 75
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (480 KB)

    Wafer-scale integration architecture for rapid prototyping (WARP), a generalized architecture for rapid prototyping, is discussed. The primary goal of rapid prototyping is to map one of several members of a class of algorithms using a single-wafer architecture. The wafer can be personalized for the algorithm by either soft or hard-restructuring. The WARP wafer consists of an array of two types of ... View full abstract»

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Computer, the flagship publication of the IEEE Computer Society, publishes peer-reviewed articles written for and by computer researchers and practitioners representing the full spectrum of computing and information technology, from hardware to software and from emerging research to new applications. 

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Editor-in-Chief
Sumi Helal
University of Florida
sumi.helal@computer.org