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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 5 • Date May 1992

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Displaying Results 1 - 12 of 12
  • Efficiently computing communication complexity for multilevel logic synthesis

    Publication Year: 1992, Page(s):545 - 554
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (744 KB)

    A new method for computing the communication complexity of a given partitioning whose running time is O(pq), where p is the number of implicants (cubes) in the minimum covering of the function and q is the number of different overlapping of those cubes, is presented. Two heuristics for finding a good partition which give encouraging results are presented. Together, these... View full abstract»

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  • Hierarchical topological sorting of apparent loops via partitioning

    Publication Year: 1992, Page(s):607 - 619
    Cited by:  Papers (2)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (872 KB)

    Topological sorting (rank ordering) is a highly useful technique for ordering a set of objects according to a precedence relation, producing an ordered list suitable for processing. Applications for topological sorting include compiled logic simulation and timing analysis. While topological sorting is easily accomplished for flat combinational logic networks, hierarchical logic can be difficult to... View full abstract»

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  • IC defect sensitivity for footprint-type spot defects

    Publication Year: 1992, Page(s):638 - 658
    Cited by:  Papers (63)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1888 KB)

    While it is important to exhaustively verify IC designs for their functional performance, it is equally important to verify their robustness against spot defects, that is, to foresee what will happen to the design when it is exposed to defect conditions in a real manufacturing environment. One such verification is done by extracting the layout sites where defects can induce a functional failure of... View full abstract»

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  • Newton waveform relaxation techniques for tightly coupled systems

    Publication Year: 1992, Page(s):598 - 606
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (692 KB)

    An algorithm, called Newton waveform relaxation (NWR), for solving large differential algebraic systems (DASs) that arise from circuit simulation is presented. Analytical and experimental comparisons will be made with waveform relaxation (WR), waveform relaxation Newton (WRN), and direct methods. This approach has been implemented in a circuit simulator called WCAzM and was found to be as much as ... View full abstract»

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  • A compiled-code hardware accelerator for circuit simulation

    Publication Year: 1992, Page(s):555 - 565
    Cited by:  Papers (8)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (940 KB)

    Describes the application of compiled-code techniques to the design of a hardware accelerator for circuit simulation, offering a speedup by a factor of up to 4400 compared with a software circuit simulator running on a Sun-3/60 workstation. The preprocessing algorithms are designed for high speed, so overall simulation time is improved by a factor of up to 560. Compiled-code hardware accelerators ... View full abstract»

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  • A detailed router for field-programmable gate arrays

    Publication Year: 1992, Page(s):620 - 628
    Cited by:  Papers (65)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (732 KB)

    A detailed routing algorithm, called the coarse graph expander (CGE), that has been designed specifically for field-programmable gate arrays (FPGAs) is described. The algorithm approaches this problem in a general way, allowing it to be used over a wide range of different FPGA routing architectures. It addresses the issue of scarce routing resources by considering the side effects that the routing... View full abstract»

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  • Design and test rules for CMOS circuits to facilitate IDDQ testing of bridging faults

    Publication Year: 1992, Page(s):659 - 670
    Cited by:  Papers (29)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (964 KB)

    All possible bridging faults (BFs) between any two circuit nodes are considered, where a circuit node may be the drain, source, or gate terminal of a transistor. Several examples are given to show that under certain circumstances current supply monitoring (CSM) cannot give correct test results. A circuit partitioning model is described, and a minimal set of design and test rules is presented. This... View full abstract»

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  • On exponential fitting for circuit simulation

    Publication Year: 1992, Page(s):566 - 574
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (688 KB)

    The stability and accuracy properties of exponentially fit integration algorithms applied to the test problem x˙=-Ax are compared with the more standard backward-Euler and semi-implicit methods. For the analysis, A∈IRn×n is assumed to be connectedly diagonally dominant with positive diagonals, as this models the equations resulting from the way ... View full abstract»

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  • A numerical model for two-dimensional transient simulation of amorphous silicon thin-film transistors

    Publication Year: 1992, Page(s):629 - 637
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (628 KB)

    A model based on a linearized solution of the Shockley-Read-Hall trapping expressions is presented. It allows these equations to be eliminated from the system matrix. This results in significantly reduced memory requirements and execution times. To illustrate the approach, the switch-on and switch-off transients of a thin-film transistor were simulated. These results are compared with ones obtaine... View full abstract»

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  • Comparison of iterative methods for AC analysis in PISCES-IIB

    Publication Year: 1992, Page(s):671 - 673
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (236 KB)

    The implementation of an improved small-signal AC simulation capability in the general-purpose device simulator PISCES-IIB is described. The preconditioned generalized conjugate residual (GCR) algorithm has been implemented, which allows AC simulations to be performed up to any frequency without convergence problems, although at great computational expense. The current implementation of PISCES-IIB... View full abstract»

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  • M3-a multilevel mixed-mode mixed A/D simulator

    Publication Year: 1992, Page(s):575 - 585
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (844 KB)

    A unified multilevel mixed-mode simulation capability for mixed analog/digital integrated circuits is described. First, a methodology for describing arbitrary analog or mixed analog/digital blocks at the behavioral level is proposed. In order to verify such models, a verification tool has been developed. The tools modgens and modgenz convert transfer functions H(s) and H(z), respectively, into sta... View full abstract»

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  • Pole and zero sensitivity calculation in asymptotic waveform evaluation

    Publication Year: 1992, Page(s):586 - 597
    Cited by:  Papers (21)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (772 KB)

    Asymptotic waveform evaluation (AWE) is a new method for approximating the behavior of linear(ized) circuits in either the time or the frequency domain in terms of a dominant pole/zero approximation. An efficient method for calculating the sensitivities of the poles and zeros found by AWE has been developed. Using the adjoint sensitivity method, it is possible to inexpensively compute the sensitiv... View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu