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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 5 • Date May 1992

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Displaying Results 1 - 12 of 12
  • Design and test rules for CMOS circuits to facilitate IDDQ testing of bridging faults

    Publication Year: 1992 , Page(s): 659 - 670
    Cited by:  Papers (23)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (964 KB)  

    All possible bridging faults (BFs) between any two circuit nodes are considered, where a circuit node may be the drain, source, or gate terminal of a transistor. Several examples are given to show that under certain circumstances current supply monitoring (CSM) cannot give correct test results. A circuit partitioning model is described, and a minimal set of design and test rules is presented. This set of rules is minimal in the sense that if any one of these rules is removed, then circuits exist for which CSM cannot give correct test results. When all the rules are satisfied it can be formally shown that: (1) all signal irredundant BFs can be detected by single vector tests, and (2) a test vector that detects a single bridging fault f1 also detects all multiple BFs that contain f1. To enhance the applicability of CSM, test and/or design strategies for dealing with circuits that do not satisfy each rule are proposed. Such circuits include a special exclusive OR gate, BiCMOS circuits, domino logic, synchronous sequential circuits, and circuits implemented by the silicon on insulator (SOI) technology View full abstract»

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  • Comparison of iterative methods for AC analysis in PISCES-IIB

    Publication Year: 1992 , Page(s): 671 - 673
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (236 KB)  

    The implementation of an improved small-signal AC simulation capability in the general-purpose device simulator PISCES-IIB is described. The preconditioned generalized conjugate residual (GCR) algorithm has been implemented, which allows AC simulations to be performed up to any frequency without convergence problems, although at great computational expense. The current implementation of PISCES-IIB uses the block successive overrelaxation algorithm for AC simulations. This algorithm fails at high frequencies, thus making it impossible to determine accurately the cutoff frequency and switching speed of high-frequency devices. The preconditioned GCR algorithm has been implemented using two different preconditioners. A comparison of the three methods shows that they are most efficient at different frequency ranges, allowing programming of an automatic switching algorithm that chooses the most efficient simulation method View full abstract»

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  • Hierarchical topological sorting of apparent loops via partitioning

    Publication Year: 1992 , Page(s): 607 - 619
    Cited by:  Papers (2)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (872 KB)  

    Topological sorting (rank ordering) is a highly useful technique for ordering a set of objects according to a precedence relation, producing an ordered list suitable for processing. Applications for topological sorting include compiled logic simulation and timing analysis. While topological sorting is easily accomplished for flat combinational logic networks, hierarchical logic can be difficult to order because feedback may appear in the hierarchical representation even though it is not present in an equivalent flattened representation. This paper presents a new general solution to this problem and describes an efficient algorithm for topological sorting even in the presence of such apparent loops. Its application to hierarchical functional simulation of combinational and synchronous sequential logic is also discussed View full abstract»

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  • A detailed router for field-programmable gate arrays

    Publication Year: 1992 , Page(s): 620 - 628
    Cited by:  Papers (54)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (732 KB)  

    A detailed routing algorithm, called the coarse graph expander (CGE), that has been designed specifically for field-programmable gate arrays (FPGAs) is described. The algorithm approaches this problem in a general way, allowing it to be used over a wide range of different FPGA routing architectures. It addresses the issue of scarce routing resources by considering the side effects that the routing of one connection has on another, and also has the ability to optimize the routing delays of time-critical connections. CGE has been used to obtain excellent routing results for several industrial circuits implemented in FPGAs with various routing architectures. The results show that CGE can route relatively large FPGAs in very close to the minimum number of tracks as determined by global routing, and it can successfully optimize the routing delays of time-critical connections. CGE has a linear run time over circuit size View full abstract»

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  • A numerical model for two-dimensional transient simulation of amorphous silicon thin-film transistors

    Publication Year: 1992 , Page(s): 629 - 637
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (628 KB)  

    A model based on a linearized solution of the Shockley-Read-Hall trapping expressions is presented. It allows these equations to be eliminated from the system matrix. This results in significantly reduced memory requirements and execution times. To illustrate the approach, the switch-on and switch-off transients of a thin-film transistor were simulated. These results are compared with ones obtained from the full two-dimensional transient numerical model. It is shown that the linearized model can simulate a wide variety of device behavior, providing close agreement with the full model at a fraction of the cost View full abstract»

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  • M3-a multilevel mixed-mode mixed A/D simulator

    Publication Year: 1992 , Page(s): 575 - 585
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (844 KB)  

    A unified multilevel mixed-mode simulation capability for mixed analog/digital integrated circuits is described. First, a methodology for describing arbitrary analog or mixed analog/digital blocks at the behavioral level is proposed. In order to verify such models, a verification tool has been developed. The tools modgens and modgenz convert transfer functions H(s) and H(z), respectively, into state space representations in the time domain and generate behavioral models. Thus, the methodology allows digital, analog, and mixed analog/digital subcircuits to be described at various levels. While the analog portions of the circuit are simulated with high accuracy, the digital portions can be simulated in various models. Simulation is event-driven. For the behavioral analog models, block elimination with unique reordering and pivoting techniques are used to accommodate state variables. This capability has been integrated into the MOTIS3 design verification system. The simulation of representative mixed analog/digital simulation examples is described View full abstract»

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  • A compiled-code hardware accelerator for circuit simulation

    Publication Year: 1992 , Page(s): 555 - 565
    Cited by:  Papers (7)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (940 KB)  

    Describes the application of compiled-code techniques to the design of a hardware accelerator for circuit simulation, offering a speedup by a factor of up to 4400 compared with a software circuit simulator running on a Sun-3/60 workstation. The preprocessing algorithms are designed for high speed, so overall simulation time is improved by a factor of up to 560. Compiled-code hardware accelerators offer several advantages. The hardware is simpler than fully hard-wired accelerators. The simplicity of the hardware makes it possible to track advancing implementation technology and to maintain the performance advantage as technology improves. The simulation algorithm is implemented in software, making it possible to implement and maintain multiple algorithms without hardware modifications. The hardware can be used efficiently, since compiled-code techniques can eliminate or statically perform operations that would be repeatedly performed in other hard-wired implementations View full abstract»

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  • Pole and zero sensitivity calculation in asymptotic waveform evaluation

    Publication Year: 1992 , Page(s): 586 - 597
    Cited by:  Papers (16)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (772 KB)  

    Asymptotic waveform evaluation (AWE) is a new method for approximating the behavior of linear(ized) circuits in either the time or the frequency domain in terms of a dominant pole/zero approximation. An efficient method for calculating the sensitivities of the poles and zeros found by AWE has been developed. Using the adjoint sensitivity method, it is possible to inexpensively compute the sensitivities of the poles and zeros with respect to all circuit parameters, as well as to suppressed circuit parasitics. The sensitivities of the approximate poles and zeros found by AWE show excellent correlation with those of the real circuit and provide useful information in both the time and the frequency domain View full abstract»

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  • On exponential fitting for circuit simulation

    Publication Year: 1992 , Page(s): 566 - 574
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (688 KB)  

    The stability and accuracy properties of exponentially fit integration algorithms applied to the test problem x˙=-Ax are compared with the more standard backward-Euler and semi-implicit methods. For the analysis, A∈IRn×n is assumed to be connectedly diagonally dominant with positive diagonals, as this models the equations resulting from the way MOS transistors and interconnect parasitics are treated in circuit-level timing simulation programs. Examples are used to demonstrate that all the exponential-fitting methods, and the semi-implicit methods, are much less accurate than backward-Euler for tightly coupled stiff problems, and an example is given which destabilizes one of the exponential-fitting methods. It is then proved that in the limit of large time steps, the more stable exponential-fitting methods become equivalent to a semi-implicit algorithm. It is shown that the backward-Euler, semi-implicit, and certain exponentially fit algorithms are multirate A-stable View full abstract»

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  • Newton waveform relaxation techniques for tightly coupled systems

    Publication Year: 1992 , Page(s): 598 - 606
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (692 KB)  

    An algorithm, called Newton waveform relaxation (NWR), for solving large differential algebraic systems (DASs) that arise from circuit simulation is presented. Analytical and experimental comparisons will be made with waveform relaxation (WR), waveform relaxation Newton (WRN), and direct methods. This approach has been implemented in a circuit simulator called WCAzM and was found to be as much as three times faster than a direct method and always faster than waveform relaxation Newton for the circuits benchmarked. Improvements to the convergence of the linear inner loop of the NWR algorithm are discussed View full abstract»

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  • Efficiently computing communication complexity for multilevel logic synthesis

    Publication Year: 1992 , Page(s): 545 - 554
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (744 KB)  

    A new method for computing the communication complexity of a given partitioning whose running time is O(pq), where p is the number of implicants (cubes) in the minimum covering of the function and q is the number of different overlapping of those cubes, is presented. Two heuristics for finding a good partition which give encouraging results are presented. Together, these two techniques allow a much larger class of functions to be synthesized. Two heuristic partitioning methods have been tested for certain circuits from the MCNC benchmark set. Using either heuristic, 11 out of 14 examples actually achieve the optimal solutions. A prototype program designed using the above techniques was developed and tested for circuits from the MCNC benchmark set. The experiment shows that the new symbolic manipulation technique is several orders of magnitude faster than an old version View full abstract»

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  • IC defect sensitivity for footprint-type spot defects

    Publication Year: 1992 , Page(s): 638 - 658
    Cited by:  Papers (61)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1888 KB)  

    While it is important to exhaustively verify IC designs for their functional performance, it is equally important to verify their robustness against spot defects, that is, to foresee what will happen to the design when it is exposed to defect conditions in a real manufacturing environment. One such verification is done by extracting the layout sites where defects can induce a functional failure of the design. Initial attempts to perform this verification task were based on a `critical area extraction' of one layer at a time, neglecting the electrical significance of interrelationships between layers. A novel method to construct deterministically multilayer critical areas is presented. These critical areas are established on the theoretical basis of defect semantics and on the new concept of `susceptible sites'. A system comprising several algorithms which in principle maintain simultaneously as many scan lines as the number of layers, in such a way that it is possible to keep track of the vertical and horizontal effects of defects, is developed View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the areas of computer-aided design of integrated circuits and systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu