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Electron Devices, IEEE Transactions on

Issue 4 • Date Apr 1992

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Displaying Results 1 - 25 of 38
  • An ultrasensitive silicon pressure-based microflow sensor

    Publication Year: 1992 , Page(s): 825 - 835
    Cited by:  Papers (14)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1016 KB)  

    An ultrasensitive silicon pressure-based flowmeter has been developed for use in measuring sub-SCCM gas flow in semiconductor process equipment. The device utilizes a capacitive pressure sensor to measure the pressure drop induced by flow across a micromachined silicon flow channel. The flowmeter is fabricated using a single-sided dissolved-wafer process and requires only six masks. The capacitive pressure sensor uses a thin (2.9 μm) stress-compensated membrane, which enables the sensor to monitor differential pressures as low as 1 mtorr while withstanding overpressures greater than 700 torr. Creep and fatigue change the offset by <0.2% full scale and alter the pressure sensitivity by <0.03 fF/mtorr; the hysteresis observed on all devices has also been <0.2% full scale, where `full scale' is defined to be the pressure required to deflect the membrane half the gap distance. The results reported indicate that it may be possible to extend the pressure range of these devices by an order of magnitude beyond full scale View full abstract»

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  • Influence of high substrate doping levels on the threshold voltage and the mobility of deep-submicrometer MOSFETs

    Publication Year: 1992 , Page(s): 932 - 938
    Cited by:  Papers (34)  |  Patents (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (624 KB)  

    The high levels of substrate doping needed in deep-submicrometer MOS devices affect device properties strongly. The authors present a detailed experimental study of high-doping effects on the threshold voltage, which is shown to be affected by the quantum-mechanical splitting of the energy levels in the conduction band. A simple expression to account for these effects is proposed and the consequences for device scaling and design are discussed. Furthermore, the increasing levels of substrate doping and high normal electric fields affect the channel mobility through Coulomb and surface-roughness scattering. Several empirical models for the surface mobility are compared with the characteristics of experimental devices View full abstract»

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  • Internal stress compensation and scaling in ultrasensitive silicon pressure sensors

    Publication Year: 1992 , Page(s): 836 - 842
    Cited by:  Papers (18)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (788 KB)  

    The pressure sensitivity of boron-doped silicon membranes has been characterized as a function of diaphragm dimensions and internal membrane stress. Using an electrostatic technique based on silicon microbridges, the internal stress for p++ silicon (on glass), LPCVD silicon dioxide, and LPCVD silicon nitride was measured; typical values are 40, -300, and 950 MPa, respectively. Silicon membranes with several different edge lengths and deposited oxide and/or nitride coatings were characterized for sensitivity. While the pressure sensitivity can be reduced by more than a factor of twenty in the membranes due to boron-induced internal stress, the use of stress-compensating dielectrics can improve this sensitivity by a factor of six or more. Based on this theory and the measured material parameters, scaled experimental devices show typical sensitivities within 10-20% of the theoretical design targets. Pressure sensitivities as high as 2900 ppm/Pa have been achieved View full abstract»

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  • CMOS-compatible lateral bipolar transistor for BiCMOS technology. I. Modeling

    Publication Year: 1992 , Page(s): 948 - 951
    Cited by:  Papers (2)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (340 KB)  

    A CMOS-compatible lateral bipolar transistor having neither an epitaxial layer nor n+-buried layers is proposed. The simulation indicates that the BiCMOS gate delay time shows a weak dependence on the metallurgical base width WB, (and hence on fTmax, since fT∝1/ WB2) and strong dependence on the effective base width WB(eff), where WB(eff) nearly equals the distance between the emitter and the n+ collector, dE-C. This is because bipolar transistors in BiCMOS circuits are operated in high-level injection during the switching transient. Therefore, it is possible to build a high-speed BiCMOS gate using lateral bipolar devices with short dE-C. The transistor has a structure similar to that of an n-channel MOSFET. The emitter and collector are formed simultaneously and self-aligned to a polysilicon base electron like the source and drain in a MOSFET View full abstract»

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  • The low-temperature behavior of thyristors

    Publication Year: 1992 , Page(s): 1011 - 1013
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (276 KB)  

    The forward breakover voltage and forward conduction voltage drop of a thyristor have been measured as a function of decreasing temperature between 25°C and -180°C. These data are presented for a 1200-V, 560-A average, inverter thyristor. Both the measured and calculated forward breakover voltages exhibit negative temperature coefficients. The decrease in VBF at low temperatures necessitates that thyristors with overrated blocking voltages be used at these temperatures View full abstract»

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  • The impact of three-dimensional effects on EEPROM cell performance

    Publication Year: 1992 , Page(s): 843 - 850
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (668 KB)  

    Device simulation is used to investigate three-dimensional effects in small electrically erasable programmable read-only memory (EEPROM) cells. Threshold voltage, tunnel currents, write speed, and the effects of misregistration are characterized for a structurally parameterized generic FLOTOX EEPROM cell. The results indicate considerable sensitivity to three-dimensional effects. Design insights for small EEPROM cells are discussed View full abstract»

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  • Parameters for optimization of device productivity at wafer level

    Publication Year: 1992 , Page(s): 952 - 958
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (552 KB)  

    The parameters that affect the productivity-wafer size, design system, levels of vertical integration, minimum feature dimension, chip size, and defect density-are examined. Expressions in terms of these parameters are given for the chip size that optimizes productivity at the wafer level. Figures of merit are shown for determination of the optimal design point View full abstract»

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  • DIBL in short-channel NMOS devices at 77 K

    Publication Year: 1992 , Page(s): 908 - 915
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (684 KB)  

    Detailed experimental and two-dimensional numerical simulation results on drain-induced barrier lowering (DIBL) versus channel length at 300 and 77 K in short-channel NMOS devices are presented. It is found that by decreasing the temperature from 300 to 77 K. DIBL in NMOS devices with effective channel lengths (L) from 0.5 to 2.0 μm is improved for the range of L<0.6 μm and L>1.2 μm, but is worse for L between 0.6 and 1.2 μm. The new version of the two-dimensional device numerical simulation program MINIMOS 4.0, which includes device modeling at cryogenic temperatures, was used to investigate this unique characteristic. The measured DIBL characteristics can be explained physically as the transition from surface DIBL through the subsurface DIBL to the bulk DIBL or punchthrough effect at 300 K, but almost a surface DIBL for the whole range of channel length variation at 77 K. Design considerations for the channel doping profile for low-temperature operation based on keeping the same DIBL and VTH as required for room-temperature operation are briefly discussed View full abstract»

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  • Detailed analysis of edge effects in SIMOX-MOS transistors

    Publication Year: 1992 , Page(s): 874 - 882
    Cited by:  Papers (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (724 KB)  

    A comprehensive investigation of edge effects in LOCOS-isolated silicon-on-insulator devices is made by combining the measurements of the static characteristics, charge pumping, and noise. Even when a substrate bias is used to mask the conduction on the island edges, the high-frequency edge effects are still detectable. Appropriate models are proposed to separate the edge contribution from those of the front and back interfaces. It is found that the defect density on the edges is inhomogeneous, increasing vertically from the top to the bottom of the film and laterally from the middle to the end of the channel. Slow traps are identified at the back interface, close to the source/drain junctions View full abstract»

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  • Accurate modeling of the source resistance in modulation-doped FETs

    Publication Year: 1992 , Page(s): 1013 - 1017
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (348 KB)  

    A distributed multiple-layer transmission line (MTL) model has been developed for the source and drain ohmic contacts of modulation-doped FETs. Results based on the authors' model clearly demonstrate that the source resistance in MODFETs cannot be estimated simply from a knowledge of the behavior of the series resistance in nongated TLM test structures. Differences between the results based on the MTL model and those obtained from the previously used lump-element contact end-resistance (LECR) model are explained View full abstract»

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  • Hole trapping during low gate bias, high drain bias hot-carrier injection in n-MOSFETs at 77 K

    Publication Year: 1992 , Page(s): 851 - 857
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (632 KB)  

    Injection and trapping of holes in the gate oxide of n-channel MOS transistors during operation at large drain and small gate biases are investigated at liquid-nitrogen temperature. Experimental evidence is given that about three times less trapping of holes occurs in the gate oxide at 77 K as compared to 295 K. The authors show that this is due to the small hole mobility in SiO2 at low temperature View full abstract»

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  • Modeling of practical multi-octave-band helical slow-wave structures of a traveling-wave tube for interaction impedance

    Publication Year: 1992 , Page(s): 996 - 1002
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (448 KB)  

    A theoretical model is developed for evaluating the interaction impedance of practical helical slow-wave structures which are anisotropically and/or inhomogeneously loaded specially for multioctave bandwidths. The discrete supports have been azimuthally smoothed out into a number of dielectric tubes of different permittivity values, while the metal vanes have been modeled by an axially conducting cylinder suitably located in the structure View full abstract»

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  • A graphical method to determine the generation parameters from pulsed MIS capacitors

    Publication Year: 1992 , Page(s): 1009 - 1011
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (264 KB)  

    A graphical method for the determination of semiconductor generation parameters has been developed. This technique is based on two graphs which are plotted from a general expression of capacitance-time ( C-t) behavior and a measured C-t curve of a pulsed metal-insulator-semiconductor capacitor (MIS-C). The generation lifetime and the surface generation velocity obtained by this method agree very well with those obtained by the Zerbst technique View full abstract»

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  • A planar interconnection technology utilizing the selective deposition of tungsten-multilevel implementation

    Publication Year: 1992 , Page(s): 901 - 907
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (728 KB)  

    The increases in crosstalk disturbance, signal delay, and current density as interconnections are scaled have been examined through simulations. Interconnections will greatly degrade the performance of integrated circuits if the metal pitch is reduced to much below 2 μm. An alternative to achieve the continuous demand in increasing the interconnection density is to add multiple layers of metallization. A tungsten interconnection technology, which inherently preserves a flat wafer surface, as well as providing frameless and stacked vias, has been demonstrated. Electrical characterization and limitations of the technology are discussed View full abstract»

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  • A high-performance 0.25-μm CMOS technology. I. Design and characterization

    Publication Year: 1992 , Page(s): 959 - 966
    Cited by:  Papers (34)  |  Patents (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (636 KB)  

    A high-performance 0.25-μm-channel CMOS technology is designed and characterized. The technology utilizes n+ polysilicon gates on nFETs and p+ polysilicon gates on pFETs so that both FETs are surface channel devices. The gate oxide thickness is 7 nm. Abrupt As and B source/drain junctions with reduced power supply voltage are used to achieve high-speed operation. The technology yields a loaded ring oscillator (NAND, FI=FO=3, Cw=0.2 pF) delay per stage of 280 ps at Weff/Leff=15 μm/0.25 μm, which is a 1.7× improvement over 0.5-μm CMOS technology. At a channel length of 0.18 μm, a CMOS stage delay of 38 ps for unloaded inverter and 185 ps for loaded NAND ring oscillators were measured. Key design issues of the CMOS devices are discussed View full abstract»

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  • Characteristics of field-induced-drain (FID) poly-Si TFTs with high on/off current ratio

    Publication Year: 1992 , Page(s): 916 - 920
    Cited by:  Papers (20)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (336 KB)  

    The characteristics of polycrystalline silicon thin-film transistors (poly-Si TFTs) with a field-induction-drain (FID) structure using an inversion layer as a drain are investigated. The FID structure not only reduces the anomalous leakage current, but also maintains a high on current. An off current of 1.5 pA/μm and an on/off current ratio of 107 (Vd=10, Vg =-20 V) are successfully obtained. These characteristics result from good junction characteristics between the p channel and n+ inversion layer. Reducing the threshold voltage of the FID region allows a simple circuit configuration for the FID TFTs View full abstract»

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  • Modeling H+-sensitive FETs with SPICE

    Publication Year: 1992 , Page(s): 813 - 819
    Cited by:  Papers (21)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (480 KB)  

    A generalized physical model including two kinds of binding sites is presented on H+-sensitive ISFET devices. The model results in a set of equations which is introduced into a modified version of the electronic circuit simulation program SPICE. In this way, the effects induced on the device performances by varying several physico-chemical parameters are analyzed. The slope of Vout versus pH curves is predicted for SiO2-, Al2O3-, and Si 3N4-gate ISFETs. The model is then used to predict the behavior of a hypothetical, partially pH-insensitive (REFET) structure. Finally, the model is utilized to fit the slow response of the Al2O3-gate ISFET to a pH stop View full abstract»

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  • High-performance plasma display panel with cathodes in the cell walls

    Publication Year: 1992 , Page(s): 803 - 808
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (568 KB)  

    An improved color DC plasma display structure was developed and its characteristics were investigated. The configuration of the device is formed using a multiple thick-film printing technique which allows the realization of a large-scale panel. Discharge occurs from thick cathodes formed on three of the cell sidewalls. The panel developed exhibits the following improvements when compared to a conventional panel with straight row-and-column electrodes: it generates a high luminous efficiency of 0.16 lm/W (a 1.3-fold improvement with a 200-μA/cell), produces high uniformity in light output (a 1.4-fold improvement), and has an increased lifetime under accelerated conditions of 240 h at 400 μA/cell (corresponding to a 4-fold improvement at 70% of initial brightness). The mechanisms of the improvements used in the new cathode structure are discussed View full abstract»

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  • GaAs bipolar transistors with a Ga0.5In0.5P hole barrier layer and carbon-doped base grown by MOVPE

    Publication Year: 1992 , Page(s): 753 - 756
    Cited by:  Papers (8)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (368 KB)  

    GaAs bipolar transistors with a 50-Å-thick lattice matched Ga0.5In0.5P layer between the emitter and base acting as a hole repelling potential barrier in the valence band were fabricated from films grown by metalorganic vapor phase epitaxy (MOVPE). The 1000-Å-thick base was doped with carbon to 2×1019 cm-3, resulting in a base sheet resistance of 250 Ω/□. Carbon has been chosen because of its low diffusivity. Using the barrier layer as an etch stop the authors fabricated mesa-type broad-area devices. The output characteristics of the devices are ideal with very small offset voltages and infinite Early voltages. Common emitter current gains of up to 70 at 104 A/cm2 collector current density were obtained. The current gain is clearly higher than the one calculated for a bipolar junction transistor with the same doping profile because the base-emitter hole current is suppressed by the Ga0.5In0.5P potential barrier in the valence band View full abstract»

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  • Theory and design methodology for an optimum single-phase CCD

    Publication Year: 1992 , Page(s): 864 - 873
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (740 KB)  

    The authors present a theory, a design methodology, and a transient simulator for a silicon single-phase CCD. The time-varying distribution of the surface hole charge is derived and an expression for maximum bias transition rate is established. The new design methodology to maximize signal capacity through nonlinear optimization is presented. The optimizer utilizes one-dimensional device models which have been corrected for small-geometry effects. The effect of parameter variation on signal capacity is assessed. A transient simulator for signal transfer is presented which accurately models fringing fields and thermal diffusion. Signal transfer speed variations with device design and geometry are discussed View full abstract»

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  • Low-noise characteristics of pulse-doped GaAs MESFETs with planar self-aligned gates

    Publication Year: 1992 , Page(s): 771 - 776
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (652 KB)  

    The authors report on the low-noise characteristics of pulse-doped GaAs MESFETs. The pulse-doped structure consists of an undoped GaAs buffer layer, a highly doped thin GaAs active layer, and an undoped GaAs cap layer grown by organometallic vapor phase epitaxy. Even though the electron mobility of this structure is 1500 cm2/V-s, the noise figures obtained are 0.72 dB at 12 GHz and 1.15 dB at 18 GHz. In addition, the noise figures are insensitive to the drain current. It was found that the noise characteristics improve as the active layer of the pulse-doped MESFET becomes thinner. These mechanisms can explain the cancellation effect between the drain noise current and gate-induced noise current as reported for HEMTs View full abstract»

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  • The effect of temperature on lateral DMOS transistors in a power IC technology

    Publication Year: 1992 , Page(s): 990 - 995
    Cited by:  Papers (12)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (516 KB)  

    A systematic study of the effects of elevated temperature on the lateral DMOS power transistors is presented. A comprehensive experimental characterization of the important LDMOS electrical parameters over the temperature range 30-300°C is reported. Simple, analytic models are used to explain the observed behavior and to offer physical insight into the effects of temperature on LDMOS performance. A novel test structure is utilized to unambiguously separate channel-region effects from drift-region effects. Using this structure it is shown that the LDMOS channel mobility follows a T-2.5 temperature dependence, which is significantly more severe than the T-1.5 dependence of conventional CMOS channel mobility. Other key temperature-dependent parameters include the threshold voltage, on-state resistance, saturation current, breakdown voltage, and leakage current, which is shown to place a fundamental limitation on the high-temperature operation of the LDMOS transistor View full abstract»

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  • An analytical delayed-turn-off model for buried-channel PMOS devices operating at 77 K

    Publication Year: 1992 , Page(s): 939 - 947
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (604 KB)  

    A closed-formed analytical PMOS delayed-turn-off model suitable for simulation of circuits with buried-channel PMOS devices operating in the delayed-turn-off region at liquid-nitrogen temperature is presented. As verified by low-temperature PISCES results, the closed-form analytical PMOS delayed-turn-off model provides a much better accuracy for simulation of circuits operating at 77 K View full abstract»

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  • Heavily doped GaAs(Be)/GaAlAs HBTs grown by MBE with high device performances and high thermal stability

    Publication Year: 1992 , Page(s): 767 - 770
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (376 KB)  

    In this study, the increase of V/III flux ratio combined with a low growth temperature has been found to lead to a drastic improvement of the HBT current gain, and also to avoid the base dopant (Be) diffusion during high post-growth process annealing. The optimized growth conditions have made it possible to obtain a very high value (70) for the maximum current gain with a base sheet resistance of 145 Ω/□, for heavily doped base HBT devices processed with a conventional low-temperature double-mesa technology. The authors have also demonstrated operational heavily doped HBT devices processed with an implanted high-temperature technology and exhibiting a DC current gain as high as 30 View full abstract»

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  • Spatial integration of direct band-to-band tunneling currents in general device structures

    Publication Year: 1992 , Page(s): 976 - 981
    Cited by:  Papers (5)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (520 KB)  

    A simplified integration technique for direct band-to-band tunneling current calculation in semiconductor devices of 1- or 2-D general device structures is described. The integration, along part of the depletion region, is of a tunneling generation function which depends on the local electric field. The simplified integration scheme relies on Kane's parabolic shaped gap barrier which accurately applies to such narrow-bandgap semiconductors as InSb and Hg1-xCdxTe. Tunneling current and zero bias resistance calculations in 1-D Hg1-xCdxTe p-n junctions using the proposed technique are presented. The extension of the technique to 2-D potential structures is demonstrated by modeling peripheral surface tunneling currents. The results compare well with measured reverse breakdown currents of InSb gate-controlled diodes View full abstract»

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IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Acting Editor-in-Chief

Dr. Paul K.-L. Yu

Dept. ECE
University of California San Diego