IEEE Transactions on Computers

Issue 8 • Aug. 1968

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  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1968, Page(s): c1
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  • IEEE Computer Group

    Publication Year: 1968, Page(s): c2
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  • High-Speed Fixed Memories Using Large-Scale Integrated Resistor Matrices

    Publication Year: 1968, Page(s):721 - 728
    Cited by:  Papers (8)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2572 KB)

    Abstract—A new READ-only memory design using resistive linear coupling has been developed for high-speed operation. Cost, reliability, and high-speed considerations lead to the use of large-scale integrated resistor matrices. Principles of operation, signal-to-noise ratios, circuits, and memory organization are discussed. The design and fabrication of large-scale integrated resistor matrices... View full abstract»

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  • Multiple Reflections from RC Loading of Pulse-Signal Transmission Lines

    Publication Year: 1968, Page(s):729 - 737
    Cited by:  Papers (2)
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    Abstract—An analysis is made with equations developed for the capacitive effect of RC loading with multiple reflections on pulse-signal transmission lines. The capacitive hold waveshape and hold time are described and compared with experimental results. Isolating the capacitive effect from the purely resistive case is accomplished so that this effect can be used to modify existing solutions.... View full abstract»

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  • The Linear Transformer Tree

    Publication Year: 1968, Page(s):738 - 746
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    Abstract—An analysis is made of the forms in which linear transformer trees may be operated. It is determined that in a voltage mode—voltage source configuration, a transformer tree can yield the 22<R>n</R> discrete outputs corresponding to an n-bit input word, requiring a single diode or equivalent nonlinear element per logical product. It is also shown in this configurati... View full abstract»

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  • The ILLIAC IV Computer

    Publication Year: 1968, Page(s):746 - 757
    Cited by:  Papers (264)  |  Patents (55)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1965 KB)

    Abstract—The structure of ILLIAC IV, a parallel-array computer containing 256 processing elements, is described. Special features include multiarray processing, multiprecision arithmetic, and fast data-routing interconnections. Individual processing elements execute 4×10<R>6</R> instructions per second to yield an effective rate of 109 operations per second. View full abstract»

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  • ILLIAC IV Software and Application Programming

    Publication Year: 1968, Page(s):758 - 770
    Cited by:  Papers (54)  |  Patents (29)
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    Abstract—An overview of the ILLIAC IV system is given and its software plans are discussed. View full abstract»

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  • An Algorithm for the Automatic Approximate Minimization of Boolean Functions

    Publication Year: 1968, Page(s):770 - 782
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2824 KB)

    Abstract—There are several algorithms that determine directly an irredundant normal form (INF) of a Boolean function without generating the entire set of prime implicants. These algorithms can generate solutions for the minimization problem much more rapidly than the algorithms determining minimum normal forms (MNF), and the cost of these solutions is, in many cases, very close to the minimu... View full abstract»

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  • Analog Computer Automatic Parameter Optimization of Nonlinear Control Systems with Specific Inputs

    Publication Year: 1968, Page(s):782 - 788
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1311 KB)

    Abstract—This note describes the application of sensitivity analysis techniques for the design of closed loop nonlinear systems with specific inputs. The optimization of the gains and the time constants of the various linear plants of the system as well as the design of nonlinear compensators are discussed. Sensitivity functions, which indicate the effect of variation of these parameters on ... View full abstract»

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  • Determination of Priority in Associative Memories

    Publication Year: 1968, Page(s):788 - 789
    Cited by:  Papers (11)  |  Patents (2)
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    Abstract—The problem of resolving multiple responses to a search in an associative or content-addressable memory is considered. A resolver is presented whose maximum delay is proportional to the logarithm of the size of the memory. View full abstract»

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  • On Suboptimal Sequential Pattern Recognition

    Publication Year: 1968, Page(s):789 - 792
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (874 KB)

    Abstract—In this note, three suboptimal solutions are obtained for the joint sequential feature selection and pattern classification problem. These solutions allow the comparison of two distinctly different approximations to the optimal procedure. One approximation involves simplifying assumptions on the underlying distribution of features for each pattern class, while the second involves an... View full abstract»

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  • Variable-Length Distinguishing Sequences and Their Application to the Design of Fault-Detection Experiments

    Publication Year: 1968, Page(s):792 - 795
    Cited by:  Papers (21)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (960 KB)

    Abstract—A variable-length distinguishing sequence (VLDS) is a preset distinguishing sequence X<L>0</L> such that, if the machine is started in an unknown state, the output response of the machine to some prefix of X<L>0</L> will identify the initial state. The length of the required prefix is a function of the initial state. The properties of such sequences are inves... View full abstract»

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  • An Algebraic Method for Minimizing the Number of States in an Incomplete Sequential Machine

    Publication Year: 1968, Page(s):795 - 798
    Cited by:  Papers (1)
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    Abstract—A structure of distributive lattice is defined on the set of partial coverings of a finite nonempty set. From this structure is derived an algorithm for calculating a minimal closed covering of the states in an incomplete sequential machine. View full abstract»

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  • A Light Pen for Remote Time-Shared Graphic Consoles

    Publication Year: 1968, Page(s):799 - 802
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  • The Origin of the Method of Iterated Consensus

    Publication Year: 1968, Page(s): 802
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (128 KB)

    Quine shows [2], [3] that a logical formula expressed as a sum of products may be transformed into the sum of all its prime implicants by repeated application of the following two rules. View full abstract»

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  • Contributors

    Publication Year: 1968, Page(s):803 - 804
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  • Abstracts of Current Computer Literature

    Publication Year: 1968, Page(s):805 - 817
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  • R68-36 Dataless Programming

    Publication Year: 1968, Page(s): 818
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  • R68-37 Intercommunication of Processors and Memory

    Publication Year: 1968, Page(s):818 - 819
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  • R68-38 Accurate Analog Computer Generation of Bessel Functions for Large Ranges

    Publication Year: 1968, Page(s): 819
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  • R68-39 Simulation of the Transfer Function of a Crustacean Muscle Bundle

    Publication Year: 1968, Page(s):819 - 820
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  • Information for authors

    Publication Year: 1968, Page(s): 820
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  • Blank Page

    Publication Year: 1968, Page(s): 820
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org