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Computers, IEEE Transactions on

Issue 7 • Date July 1968

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Displaying Results 1 - 25 of 27
  • IEEE Transactions on Computers - Table of contents

    Page(s): c1
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  • IEEE Computer Group

    Page(s): c2
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  • Horizons in Guidance Computer Component Technology

    Page(s): 621 - 634
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    Abstract—An extensive survey of logic and memory component manufacturers conducted by the NASA Electronic Research Center and the industry has resulted in estimates of the state-of-the-art of components available to designers of on-board guidance and control computers for long-term deep-space missions for the 1970-72 period. The vehicle for the survey were the mission requirements for the synchronous satellite, lunar orbiter, Mars orbiter, and Jupiter fly-by solar probe missions. View full abstract»

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  • A Visual Image Processor

    Page(s): 635 - 639
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    Abstract—A computer, the Visual Image Processor, is described which is designed to process visual images. Images are read by a vidicon camera and stored in any of three identical cathode-ray electrostatic storage tubes. Two storage systems are read simultaneously, with the reading beams spatially displaced from each other, and a signal which is a function of the reading signals is written into the third storage system. The spatial displacement of the reading beams and the function are variable and under control of the computer operator. View full abstract»

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  • Computer Aided Memory Design Using Transmission Line Models

    Page(s): 640 - 648
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    Abstract—This paper describes a computer program for analyzing a class of transmission line configurations which arise in the design of memory arrays. The systems analyzed by the program consist of interconnected pairs of mutually coupled distributed parameter transmission lines driven and terminated by linear lumped element networks. A brief discussion of the mathematical model and its implementation is given and applications of the program to the design of 2½D and 3D memory arrays are described. The applications illustrate how the program can be used to evaluate pulse propagation characteristics and noise generation mechanisms within a memory array. View full abstract»

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  • Convolutional Transformation and Recovery of Binary Sequences

    Page(s): 649 - 655
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    Abstract—This paper analyzes invertible length-preserving convolutional transformations of binary sequences, when the perfect inverse feedback transducer is replaced by a finite feedforward (i. e., convolutional) transducer which represents an approximation of the former. This replacement eliminates the error propagation effect, but the finiteness of the "inverse" transducer (decoder) results in a restriction on the input sequences, for which exact replication is achieved in the two-way transduction (transformation and recovery). The entity of the input restriction can be taken as a measure of performance for sets of transformations, and can be described in terms of the upper bound of the entropies of the binary sources which are "matched" to the system (direct and inverse transducers). This bound is clearly the capacity of the system viewed as a noiseless channel. It is shown that, if r is the number of decoder stages, the channel capacity has an asymptotic expression C≃1-Abr, where the parameters b < 1 and A depend solely upon the structure of the set of resynchronizing states (RS cluster) possessed by the given set of transformations. View full abstract»

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  • Variable-Threshold Threshold Elements

    Page(s): 656 - 667
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    Abstract—Variable-threshold threshold elements (V-T threshold elements) are threshold elements in which the weights are fixed while the threshold may be varied. When the threshold is varied, a set of functions is generated. View full abstract»

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  • Nets of Variable-Threshold Threshold Elements

    Page(s): 667 - 676
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    Abstract—A variable-threshold net is a network of variable-threshold threshold elements in which the threshold of all elements is a common variable parameter. Synthesis of such nets to realize a given set of functions not realizable by a single element is discussed. An application to realizing sequential machines is described. The problem of prevention of malfunction due to component drift is formalized and solved. View full abstract»

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  • Analyzing Errors with the Boolean Difference

    Page(s): 676 - 683
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    Abstract—The Boolean difference is defined. It is shown through example how the Boolean difference is used to analyze the effect of errors on the outputs of logic circuits. Examples are given of error detection problems, analysis of redundant logic, and the generation of diagnostic sequences. View full abstract»

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  • An Approach to Optimum Tolerance Adaptive Threshold Elements

    Page(s): 684 - 691
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    Abstract—A definition of the tolerance for the weights of adaptive threshold elements is given which is more relevant to the characteristics of real adaptive components. A learning procedure is then proposed, which employs a sequence of different and increasing values of dead zone. This procedure achieves the determination of the set of maximum tolerance weights and its soundness is shown by systematic tests performed by simulation on an IBM 7094 digital computer on all the binary functions of 5 variables. View full abstract»

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  • Path Finding with Associative Memory

    Page(s): 691 - 693
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    Abstract—This note discusses possible advantages to be gained through use of associative memory in finding the shortest path through a large graph having edges of unequal lengths. An algorithm is described which exploits associative memory's highly parallel search and arithmetic capabilities and which is economical in storage requirements. View full abstract»

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  • A New Algorithm for Inner Product

    Page(s): 693 - 694
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    Abstract—In this note we describe a new way of computing the inner product of two vectors. This method cuts down the number of multiplications required when we want to perform a large number of inner products on a smaller set of vectors. In particular, we obtain that the product of two n×n matrices can be performed using roughly n3/2 multiplications instead of the n3multiplications which the regular method necessitates. View full abstract»

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  • A Variable Counter Design Technique

    Page(s): 694 - 696
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    Abstract—Two design techniques are presented which allow one counter circuit to divide a fixed-reference frequency by a wide range of counts. In the examples used the output frequency is preselected on three 10-position selector switches, providing for division of the input reference frequency by N, where 1≤N≤999. The techniques described are not dependent on the type of digital logic used and are therefore applicable to any family of binary logic modules. View full abstract»

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  • On the Characterizing Parameters of a Threshold Function

    Page(s): 696 - 697
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    Abstract—A switching function A is viewed as a subset of vertices of the unit n-cube. The power parameter of A is the number of vertices comprising A and the characterizing vector is the vector sum of the vertices of A. It is shown that the characterizing vector (without the power parameter) uniquely determines a threshold function within parity. View full abstract»

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  • A Synthesis Technique for Binary Input-Binary Output Synchronous Sequential Moore Machines

    Page(s): 697 - 699
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    Abstract—A "synthesis technique" is presented for "realizing" any arbitrary binary input-binary output "synchronous sequential Moore machine" in the form of a network composed of identical 2-state "component machines." With slight modification the synthesis technique presented can be used to realize any given n-input-p-output synchronous sequential Moore machine in the form of a network composed of identical 2-state component machines. View full abstract»

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  • Two Complete Axiom Systems for the Extended Language of Regular Expressions

    Page(s): 700 - 701
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    Abstract—Two consistent and complete formal systems for the algebraic transformation of regular expressions involving intersections and complements are given. Both systems are extensions of the system F1presented in Salomaa [5]. As a result, a method of eliminating intersections and complements from regular expressions is obtained. This solves a problem proposed by Eggan. View full abstract»

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  • Comments on "RST Flip-Flop Input Equations"

    Page(s): 701 - 702
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    In a recent paper Graham and Distler1have shown how all the possible combinations of the input equations of an RST flip-flop can be displayed simultaneously on the Karnaugh maps. This claim is valid only if a1, a2on the R map and a3, a4on the S map are replaced by ai, and each aican be chosen independently of the others. Whereas, in the Graham and Distler techniques, a1chosen to be 1 (or 0) on one vertex of the Karnaugh map implies that all a1are to be 1 (or 0), and the same is true about a2, a3, and a4. View full abstract»

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  • Comments on "Basic Properties and a Construction Method for Fail-Safe Logical Systems"

    Page(s): 702
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    The paper by Mine and Kogal appears to have some unstated assumptions and inconsistencies which affect the validity of their claim to have presented "an effective method of logical design for fail-safe systems." View full abstract»

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  • Authors' Reply3

    Page(s): 702
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    In Theorem 3, it is clearly stated that the fail-safe output of a basic function is severely restricted by the failed output of the preceding basic functions (though two Iff's in the statement of Theorem 3 should be If's). It is obvious, as a matter of course, that a single failure of an element in a logical circuit may cause different effects on its following logical functions. It should be noted here that we do not deal with types of internal failures of logical circuits but with outputs of logical functions being restricted by their following logical functions. If open inputs to the terminal logic shown in Fig. 1 of Mr. Foster's comment are allowed, then the conditions in Theorem 3 are not satisfied any more. This apparently does not cause any inconsistency in our paper.1Examples of fail-safe NOR circuits shown in Section V are illustrated for the construction of fail-safe logical systems only with NOR circuits. This should have been noted in our paper. View full abstract»

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  • Contributors

    Page(s): 703 - 704
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  • Abstracts of Current Computer Literature

    Page(s): 705 - 717
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  • R68-32 The IADIC: A Hybrid Computing Element

    Page(s): 718
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  • R68-33 PHENO: A New Concept of Hybrid Computing Elements

    Page(s): 718 - 719
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  • R68-34 Hybrid Apollo Docking Simulation

    Page(s): 719
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  • R68-35 Optimal Generation of Arbitrary Functions

    Page(s): 719 - 720
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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Albert Y. Zomaya
School of Information Technologies
Building J12
The University of Sydney
Sydney, NSW 2006, Australia
http://www.cs.usyd.edu.au/~zomaya
albert.zomaya@sydney.edu.au