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Computers, IEEE Transactions on

Issue 12 • Date Dec. 1968

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Displaying Results 1 - 19 of 19
  • IEEE Transactions on Computers - Table of contents

    Page(s): c1 - 1230
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  • IEEE Computer Group

    Page(s): c2
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  • Construction of Multistep Integration Formulas for Simulation Purposes

    Page(s): 1121 - 1131
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    Abstract—Block-oriented simulation languages are a powerful tool for solving simulation problems. A problem of major importance in simulation, however, is the choice of the integration formula to be employed in the integration block. Users of early simulation languages had no difficulty selecting a formula since these languages provided only a single formula. Advanced languages have a number of formulas available, but leave the choice to the user who does not have much to go by except the good names of the formulas. Difficulties which were encountered in the use of multistep formulas made formulas of the Runge-Kutta type more popular. Experience has shown that they are less critical with respect to stability. However, the computing time for a Runge-Kutta formula is considerably larger and for this reason multistep formulas, which include the predictor- corrector scheme, are still appealing. View full abstract»

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  • Analysis of Asynchronous Circuits Under Different Delay Assumptions

    Page(s): 1131 - 1143
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    Abstract—Asynchronous circuits are analyzed from the stand- point of different constraints which may apply to the stray delays (zero-line delays, bounded delays, and the use of delay elements). The relationship between "hazard-free" sequential networks and "speed independent" circuits is illuminated. Speed independence is defined relative to a fundamental mode circuit (which in turn may be described by a flow table); the analysis is carried out from this stand- point. The allowed sequence graph may be used to detect critical races. A circuit is seen to be speed independent if and only if its circuit-derived excitation matrix has no 1-input change critical races. The generalization of the essential hazard has been studied in detail and is shown to be an obstacle to hazard-free realizations when line delays can be arbitrarily large. View full abstract»

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  • Control Storage Use in Implementing an Associative Memory for a Time-Shared Processor

    Page(s): 1144 - 1151
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    Abstract—The Cambridge System, comprising a standard IBM System/360 Model 40 and an associative memory, is described from the viewpoint of its implementation using the READ-only control storage of the Model 40. In particular, we discuss the use of the ROS in 1) controlling the flow of data between the CPU and the associative memory registers, and 2) handling translation control, absent page indications, and variable field operand pretesting, when the associative memory is used for page translation in a time-sharing mode of operation. Although the main use of the system is as a computer facility that may be shared simultaneously by up to fifteen users, it may also be used as an ordinary batch processor having a small experimental associative memory among its facilities. The magnitude of the ROS additions and modifications, in terms of numbers of microinstructions, is given. View full abstract»

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  • Sequential Decision-Making Device for Information-Processing Applications

    Page(s): 1151 - 1156
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    Abstract—This paper describes the concept of a hardware sequential decision-making device consisting principally of an array or network of nodes which can support a plurality of connections among the nodes on a simultaneous basis. The connection "chains" the nodes together. The application of the device to a dynamic computer memory allocation system is described in the paper. In this use, each "node" would correspond to a word or a group of words in a storage device, the access to which is controlled by a control unit employing the node network. Thus, only one node needs to be selected to either load a record into the controlled memory unit, or to read the record from it. View full abstract»

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  • Generalized Inverse Approach to Adaptive Multiclass Pattern Classification

    Page(s): 1157 - 1164
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    Abstract—In this paper a least-square approach to multiclass pattern classification is undertaken. The generalized inverse computation is used to furnish a quick solution to the problem of fixed training samples. The use of recursive on-line computation is also recommended. Experimental results are presented to illustrate the approach. Both deterministic and statistical interpretations have been given to the approach. The pattern classifier proposed by Chaplin and Levadi [1] and the adaptive pattern classifier proposed by Patterson and Womack [2] are special cases of this approach. View full abstract»

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  • Synthesis of Nonlinear Decision Boundaries by Cascaded Threshold Gates

    Page(s): 1165 - 1172
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    Abstract—This paper presents a technique for generating a nonlinear decision surface that separates two finite classes of elements in n-dimensional real space. It incorporates the principle of cascaded threshold gates in evolving the required separation surface. At each stage of the design, an additional cascaded gate is added which will separate at least one new element. Necessary and sufficient conditions are developed whereby one may readily determine if two new elements may be properly separated by the addition of one cascaded threshold gate. The results are illustrated by means of numerical examples. View full abstract»

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  • Near-Optimal Ordering of Electronic Circuit Equations

    Page(s): 1173 - 1174
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    Abstract—An implementation of an algorithm for near-optimal ordering of sparse network equations is described. Such ordering can result in considerable savings in computer time and may be applied to various types of analysis programs. A sample problem demonstrates a saving in computer time in excess of 50 percent. View full abstract»

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  • Ternary Cyclo-Decompositions

    Page(s): 1175 - 1176
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    Abstract—This note discusses a particular kind of ternary functional decomposition based on a ternary function ↑ to be performed on the set of composite functions. Such function is closely related to the cycling concept of Postian algebras. A systematic method is given to determine the set of all decompositions of that kind admitted by the function. Such set is called the cyclo-set and it is proved that it is a filter in the partitions lattice. Since any partition of the lattice can be expressed as an intersection of cardinality-2 partitions, it follows that the method consists merely in finding the infimum of the cardinality-2 partitions belonging to the cyclo-set and then determining the filter having this infimum as vertex. The existence of proper subsets of the cardinality-2 partitions set leading to the determination of the ifiter-vertex is discussed, and results obtained for functions of domain-order up to seven are stated. Finally, the total number of cyclo-decompositions for a given partitional structure is calculated. View full abstract»

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  • Realization of Sequential Machines

    Page(s): 1177
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  • Contributors

    Page(s): 1178 - 1179
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  • R68-51 The Design of an Automatic Patching System

    Page(s): 1179 - 1181
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  • R68-52 The Structure of the "The"-Multiprogramming System

    Page(s): 1181
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  • R68-53 A System for Interactive Graphical Programming

    Page(s): 1181 - 1182
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  • Abstracts of Current Computer Literature

    Page(s): 1183 - 1230
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  • Blank Page

    Page(s): 1230
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  • Blank Page

    Page(s): 1230
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  • Information for authors

    Page(s): 1230
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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Albert Y. Zomaya
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