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Computers, IEEE Transactions on

Issue 11 • Date Nov. 1968

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Displaying Results 1 - 23 of 23
  • IEEE Transactions on Computers - Table of contents

    Page(s): c1 - 1120
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  • IEEE Computer Group

    Page(s): c2
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  • Editor's Notice

    Page(s): 1025
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  • Announcement Transactions Available in Microfiche Form

    Page(s): 1026
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  • Process Performance Computer for Adaptive Control Systems

    Page(s): 1027 - 1037
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    Abstract—Adaptive control of complex manufacturing processes can provide significant improvements in production rate and product quality. To maximize these advantages, the adaptive control system must be capable of making accurate measurement of process per- formance. This paper describes the implementation of a general- purpose performance computer which makes use of a combination of two techniques: trainable pattern recognition and linear regression. The description covers the system concept, the training procedures or algorithms, and the detailed design. View full abstract»

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  • A Delay Line and Logic Circuits Utilizing Charge-Storage Subharmonic Parametric Oscillators

    Page(s): 1037 - 1043
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    Abstract—The charge-storage subharmonic parametric oscillator may be switched from one state to the other within one cycle of pump voltage. This property is used in the design and construction of a 6-element delay line. This delay line is shown to perform predictably when the elements are connected in a loop to give a self- switching arrangement. View full abstract»

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  • Digital System Design Automation—A Method for Designing a Digital System as a Sequential Network System

    Page(s): 1044 - 1061
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    Abstract—This paper deals with computer-aided design of digital systems and presents a formal method for designing a digital system via state tables. The steps of the design method can be summarized as follows: a) a system is described by a set of microprograms written in a "transfer language," b) the set of microprograms is translated into a set of flow tables by an algorithm, and c) the flow tables are converted into logical diagrams by synthesis procedures. The purpose of step a) is to aid the designer in describing the system; the result of step b) makes it possible to reduce the logical complexity of the system by using systematic techniques of the sequential network theory; and the result of step c) is a system of interconnected sequential networks, operating simultaneously which may include iterative asynchronous networks. View full abstract»

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  • High-Speed, Interlaced WRITE and READ-Only Operation of a Plated-Wire Memory System

    Page(s): 1062 - 1065
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    Abstract—A 1024-word by 80-digit exploratory plated-wire store using diode-matrix word selection has a cycle time of 100 ns or less for READ and 140 ns for WRITE, while the destructive READWRITE asts 150 to 200 ns. To match the fluctuation in the type of request encountered, typically 80 percent READ, and thus maximize the throughput, it is advantageous to switch memory mode in an interlaced manner at logic speed. This is done by exploiting the plated-wire properties of NDRO and fast WRITE. A charge storage diode is used for memory protection and common word current control; READ 400 mA, WRITE 900 mA. View full abstract»

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  • The Basis for Implementation of Ad idive Operations in the Residue Number System

    Page(s): 1066 - 1073
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    Abstract—A new residue number system algebra has been previously proposed by the author. The algebra has solved an essential theoretical barrier in the residue number system and has enabled one to pursue additive operations in the residue number system to their full extent, overcoming such difficulties as restrictions on the sign or magnitude of numbers in the system. In this paper, basic theorems in the algebra are introduced first, and then, based on the theorems, table look-up oriented solutions for hardware overflow checking, sign detection, and floating-point additive operations are given. The theorems expound the behavior of a quantity treated as a veiled mysterious function in the literature. To the best knowledge of the author, hardware overflow-checking schemes and floatingpoint additive operations in the residue number system have never been reported elsewhere. So far, the upper limit of the magnitude of numbers in the system ever discussed has been the one that is theory-limited, and floating-point operations in the residue number system have never been discussed. View full abstract»

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  • NORNAND Maitra Cascades

    Page(s): 1074 - 1080
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    Abstract—Maitra cascades are introduced here using two-input NAND and/or NOR. Tests for function synthesis by these kinds of cascades are introduced. The same methods can be used to design a cascade to realize a given function, when it exists. Finally, some procedutes are given for making such a cascade as short as possible. View full abstract»

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  • Some Theoretical Properties of Multithreshold Realizable Functions

    Page(s): 1081 - 1088
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    Abstract—In recent years, considerable attention has been focused on the problem of improving the logic implementation capability of logic elements in digital computer circuits. This paper investigates the theoretical properties of a logic element called the multithreshold threshold element. The concept of this logic element is a generalization of the concept of the single-threshold threshold element. View full abstract»

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  • Partitions and Edge-Weighted Pair-Graphs

    Page(s): 1089
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    Abstract—This note describes an edge-weighted pair-graph method for easily calculating the glb and lub of any two partitions on a finite set. The criterion for two partitions to be complements of one another is also easily described by use of an edge-weighted pair-graph. View full abstract»

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  • An Attempt to Design an Improved Multiplication System

    Page(s): 1090
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    Abstract—A speeded-up multiplication technique is considered wherein the two numbers to be multiplied are first examined and the one with the fewer 1's is selected as the multiplier. It is found that the speeding-up diminishes towards 0 as the word length increases. View full abstract»

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  • Comments on "An Algorithm for Synthesis of Multiple-Output Combinational Logic"

    Page(s): 1091 - 1092
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    Abstract—The principal synthesis example of Schneider and Dietmeyer's paper [1] is examined by applying a new synthesis algorithm. The minimum NOR gate realization thus obtained is used to illustrate the nonoptimality of their approach and to question their definition of delay. Arguments are advanced for synthesis with simple modules. View full abstract»

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  • A Random-Walk Model of a Queue Storage Problem

    Page(s): 1093 - 1095
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    Abstract—A probability model of queue storage allocation problems is devised and an analysis is provided based on the theory of random walks. Two types of queue storage allocation are discussed and analyzed, after which examples are given to illustrate their relative advantages and disadvantages. View full abstract»

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  • Contributors

    Page(s): 1096 - 1097
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  • R68-46 Use of Transition Matrices in Compiling

    Page(s): 1098
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  • R68-47 Computer Scheduling Methods and Their Countermeasures

    Page(s): 1098 - 1099
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  • R68-48 A Multiprogramming Monitor for Small Machines

    Page(s): 1099
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  • R68-49 Virtual Memory Processes and Sharing in Multics

    Page(s): 1099
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  • R68-50 Multiprogramming System Performance Measurement and Analysis

    Page(s): 1100
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  • Abstracts of Current Computer Literature

    Page(s): 1101 - 1120
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  • Information for authors

    Page(s): 1120
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Albert Y. Zomaya
School of Information Technologies
Building J12
The University of Sydney
Sydney, NSW 2006, Australia
http://www.cs.usyd.edu.au/~zomaya
albert.zomaya@sydney.edu.au