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Solid-State Circuits, IEEE Journal of

Issue 9 • Date Sept. 2006

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Displaying Results 1 - 25 of 27
  • [Front cover]

    Page(s): c1 - c4
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    Freely Available from IEEE
  • IEEE Journal of Solid-State Circuits publication information

    Page(s): c2
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    Freely Available from IEEE
  • Table of contents

    Page(s): 1957 - 1958
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  • A Distortion Compensating Flash Analog-to-Digital Conversion Technique

    Page(s): 1959 - 1969
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1299 KB) |  | HTML iconHTML  

    We present a flash ADC design technique that compensates for static nonlinearity of the up-front track-and-hold circuit, so that high speed and high linearity can be obtained at the same time. The proposed technique functions in synergy with a new background comparator offset correction scheme. The excess quantization noise generated due to the background autozero process is derived. We demonstrate the efficacy of our techniques with measurement results for a 160 MSPS 6-bit flash converter designed in a 0.35-mum CMOS process. The ADC consumes 50 mW from a 3.3 V power supply and has an 5.3 effective number of bits (ENOB) at Nyquist View full abstract»

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  • 1.2-V Low-Power Multi-Mode DAC+Filter Blocks for Reconfigurable (WLAN/UMTS, WLAN/Bluetooth) Transmitters

    Page(s): 1970 - 1982
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    Two versions of a baseband block composed by a 8-bit current-steering DAC and a fourth-order low-pass reconstruction filter are realized in a 0.13-mum CMOS technology to be embedded in multistandard wireless transmitters. In order to satisfy the specifications of WLAN IEEE 802.11a/b/g, UMTS, and Bluetooth standards, the proposed devices can be digitally programmed, adjusting the DAC conversion frequency and the low-pass filter cut-off frequency. For the WLAN case, the DAC operating frequency and the filter bandwidth are set to 100 MHz and 11 MHz, respectively, for the UMTS case, they are equal to 50 MHz and 2.5 MHz, and for the Bluetooth case, they are equal to 50 MHz and 1 MHz. The first device is reconfigurable between WLAN and UMTS, and the second one between WLAN and Bluetooth. The two fabricated devices operate from a single 1.2-V supply voltage and occupy a 0.8 mm 2 and 0.7 mm2 die area, respectively. The power consumption is optimized according to the operation mode and is 8 mW in WLAN mode, 8.4 mW in UMTS mode, and 5.4 mW in Bluetooth mode. For all the considered standards, the measured OIP3 is larger than 28 dBm, while the SFDR is 54 dB for WLAN, 61 dB for UMTS, and 63 dB for Bluetooth View full abstract»

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  • Low-Power Single-Loop and Dual-Loop AGCs for Bionic Ears

    Page(s): 1983 - 1996
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    Bionic ears or cochlear implants for the deaf require low-power wide-dynamic-range automatic-gain-control circuits (AGCs) to interface between microphone preamplifiers and analog processing circuits or A/D converters. Hearing-impaired patients need strategies which switch intelligently between time constants for speech and time constants for interfering transients. We describe two AGC designs which use a programmable continuous current-mode feedback network to control a variable gain amplifier. The first design implements a log-linear controller to demonstrate level-invariant closed-loop response. The second design is a dual-loop controller which implements a simplified version of a well-known algorithm for speech in noisy environments. The dual-loop strategy implements a continuous-discrete hybrid controller with implicit state control using two filter-and-hold peak detectors and a charge-pump hold-timer. Both AGCs exhibit 78 dB of input dynamic range, have digitally programmable time constants, operate from a 2.8 V supply, and consume less than 36 muW in a 1.5 mum BiCMOS process. For typical compression settings, the minimum instantaneous input dynamic range is greater than 58 dB View full abstract»

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  • A Low-Power Wideband Reconfigurable Integrated Active-RC Filter With 73 dB SFDR

    Page(s): 1997 - 2008
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    In this paper, a low-power, highly linear, integrated, active-RC filter exhibiting a reconfigurable transfer function (Chebyshev, Elliptic) and bandwidth (5 MHz, 10 MHz), is presented. The filter exploits digitally-controlled polysilicon resistor banks and a digital automatic tuning scheme to account for process and temperature variations. The operational amplifiers used are based on a new compensation technique that allows optimized high-frequency filter performance and minimized current consumption. A filter prototype has been fabricated in a 0.12-mum CMOS process, occupies 0.25 mm2 (tuning circuit included), and achieves an IIP3 of approximately +20 dBm, whereas its spurious free dynamic range (SFDR) reaches 73 dB. The dissipation of the filter core and the tuning circuit is 4.6 mW and 1.5 mW, respectively View full abstract»

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  • Nanowatt, Sub-nS OTAs, With Sub-10-mV Input Offset, Using Series-Parallel Current Mirrors

    Page(s): 2009 - 2018
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    In this paper, series-parallel (SP) current-division will be employed for the design of very low transconductance OTAs. From the theory and measurements, it will be shown that SP mirrors allow the division of currents with division factors of thousands, without reducing matching or noise performance. SP mirrors will be applied to the design of OTAs ranging from 33 pS to a few nS, with up to 1 V linear range, consuming in the order of 100nW, and with a reduced area. An integrated 3.3-s time-constant integrator will also be presented. Several design concerns will be studied: linearity, offset, noise, and leakages, as well as layout techniques. A final comparative analysis concludes that SP association of transistors allows the design of very efficient transconductors, for demanding applications in the field of implantable electronics, among others View full abstract»

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  • A 110 nA Voltage Regulator System With Dynamic Bandwidth Boosting for RFID Systems

    Page(s): 2019 - 2028
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    This paper describes a voltage regulator system for ultra-low-power RFID tags (also called passive tags) in a 0.15 mum analog CMOS technology. These tags derive their power supply from the incoming RF energy through rectification instead of from a battery. The regulator is functional with just 110 nA current. Owing to the huge variation of the rectified voltage (by as much as tens of volts), voltage limiters and clamps are employed at various points along the regulation path. A limiter at the rectifier output clamps the rectifier voltage to a narrower range of 1.4 V. A fine-regulator, then, regulates the supply voltage close to a bandgap reference value of 1.25 V. The key aspect of this regulator is the dynamic bandwidth boosting that takes place in the regulator by sensing the excess current that is bypassed in the limter (during periods of excess energy) and increasing its bias current and hence bandwidth, accordingly. A higher bandwidth is necessary for quick recovery from line transients due to the burst nature of RF transmission, with a larger energy burst requiring a higher bandwidth to settle quickly without large line transients. The challenge of compensating such a regulator across various load currents and RF energy levels is described in this paper View full abstract»

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  • 2 GHz \rm Q -Enhanced Active Filter With Low Passband Distortion and High Dynamic Range

    Page(s): 2029 - 2039
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    A tunable Q-enhanced filter with low passband distortion is presented. The Q of the on-chip spiral inductors that form the filter resonators is enhanced by using a cross-coupled differential pair which is degenerated by a second LC tank. This technique allows for frequency dependent compensation of inductor losses and ensures that the Q-enhanced LC resonators have a frequency behaviour close to the ideal in the passband of the filter. The circuit allows DC voltage control of Q-enhancement. The filter centered at 2.0 GHz with a 130 MHz bandwidth is tunable in frequency by 3%, exhibits a -6.6 dBm 1-dB compression point and a 15 dB noise figure while consuming 17 mW of DC power. The circuit was fabricated in 0.18-mum CMOS and the performance was verified experimentally View full abstract»

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  • Modeling of Substrate Noise Generation, Isolation, and Impact for an LC-VCO and a Digital Modem on a Lightly-Doped Substrate

    Page(s): 2040 - 2051
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    Substrate noise generated by the digital circuits on a mixed-signal IC can severely disturb the analog and RF circuits sharing the same substrate. Simulations at the circuit level of the substrate noise coupling in large systems-on-chip (SoCs) do not provide the necessary understanding in the problem. Analysis at a higher level of abstraction gives much more insight in the coupling mechanisms. This paper presents a physical model to estimate and understand the substrate noise generation by a digital modem, the propagation of this noise and the resulting performance degradation of LC tank VCOs. The proposed linearized model is fast to derive and to evaluate, while remaining accurate. It is validated with measurements on two test structures: a reference design and a design with a p+/n-well (digital) guard ring. Both structures contain a functional 40k gate digital modem and a 0.18 mum 3.5 GHz CMOS LC-VCO on a lightly-doped substrate. In both cases, the model accurately predicts the level of the spurious components appearing at the VCO output due to the digital switching activity. The error remains smaller than 3 dB. Finally, we demonstrate how the proposed model enables a systematic and controlled isolation strategy to suppress substrate noise coupling problems. As an example, the model is used to determine suitable dimensions for a digital guard ring View full abstract»

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  • A 12.5-Gb/s Parallel Phase Detection Clock and Data Recovery Circuit in 0.13- \mu\hbox {m} CMOS

    Page(s): 2052 - 2057
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    A clock and data recovery (CDR) architecture featuring a parallel phase detector is proposed for speeding up linear-type CDRs. A cause of speed limit in conventional CDRs is very short UP pulses in its phase detector circuit. The parallel phase detector expands UP pulsewidth by adding fixed-width using a half-rate clock. The parallel phase detector is used in the CDR with a couple of unbalanced charge-pump. The bandwidth of decision latches of the PD is extended by 1.7 times by using both shunt-peaking and capacitance coupling. The monolithic CDR implemented in 0.13-mum CMOS shows 1.7 times wider phase linear response region of 0.56UI than that of a conventional CDR. It operates at 12.5-Gb/s with PRBS 231-1 input data. Measurements show large jitter tolerance of over 0.5 UIpp for 4-8 MHz jitter frequency as well as jitter transfer characteristics independent on input-jitter amplitudes of 0.1, 0.3, and 0.5 UIpp View full abstract»

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  • A 20-Gb/s Adaptive Equalizer in 0.13- \mu\hbox {m} CMOS Technology

    Page(s): 2058 - 2066
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    An adaptive equalizer incorporates spectrum-balancing technique to achieve high speed and low power dissipation. Obviating the need for slicers, this circuit compares the low and high frequency components of the data spectrum and adjusts the boosting accordingly. Fabricated in 0.13-mum CMOS technology, this circuit achieves a data rate of 20 Gb/s while consuming 60mW from a 1.5-V supply View full abstract»

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  • A 34 Gb/s Distributed 2:1 MUX and CMU Using 0.18 \mu\hbox {m} CMOS

    Page(s): 2067 - 2076
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    A 34 Gb/s 2:1 serializer consisting of a CMOS MUX and CMU using a 0.18 mum SiGe BiCMOS process is presented. The serializer is based on distributed amplifier topology realized using spiral inductors. The circuit also includes an on-chip 2-channel 27-1 PRBS generator. The 34 Gb/s serial output has single-ended voltage swing of 380 mV with rise/fall time of 13 ps, and measured ISI is less than 5 ps p-p View full abstract»

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  • A 120-MHz–1.8-GHz CMOS DLL-Based Clock Generator for Dynamic Frequency Scaling

    Page(s): 2077 - 2082
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    A delay-locked loop (DLL)-based clock generator for dynamic frequency scaling has been developed in a 0.35-mum CMOS technology. The proposed clock generator can generate clock signals ranging from 120 MHz to 1.8 GHz and change the frequency dynamically in a short time. If the clock generator scales its output frequency dynamically by programming with the same last bit, it takes only one clock cycle to lock. In addition, the clock generator inherits advantages of a DLL. The proposed DLL-based clock generator occupies 0.07 mm2 and has a peak-to-peak jitter of plusmn6.6 ps at 1.3 GHz View full abstract»

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  • Distributed Differential Oscillators for Global Clock Networks

    Page(s): 2083 - 2094
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    This paper presents a distributed differential oscillator global clock network where the clock capacitance is rendered resonant with a set of on-chip spiral inductors. The clock amplitude and clock phase are both uniform across the entire global distribution, making this design scalable and compatible with existing local clocking methodologies. The resonant network, combined with phase averaging of the distributed oscillator, provides high immunity to process-, voltage-, and temperature-variation-induced timing uncertainty. Measurement results from a prototype design implemented in a 0.18-mum CMOS technology show almost an order of magnitude less jitter and power than a traditional tree-driven grid global clock distribution. On-chip measurement circuits are used to characterize the jitter on the test chip, while a simulation model is used to examine skew and higher-order resonances in the resonant clock network View full abstract»

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  • Extended Dynamic Range From a Combined Linear-Logarithmic CMOS Image Sensor

    Page(s): 2095 - 2106
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    A CMOS image sensor that can operate in both linear and logarithmic mode is described. Two sets of data are acquired and combined in the readout path to render a high dynamic range image. This is accomplished in real-time without the use of frame memory. A dynamic range in excess of 120 dB was achieved at 26 frames/s (352times288-array). The system addresses the problems of high fixed pattern noise (FPN), slow response time, and low signal-to-noise ratio (SNR) in logarithmic mode. FPN has been effectively reduced by single and two parameter calibration, the latter achieving FPN of 2% per decade. A novel on-chip method of deriving a reference point has been implemented. The system is fabricated in a 0.18-mum 1P4M process and achieves a pixel pitch of 5.6 mum with 7 transistors per pixel View full abstract»

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  • Adaptive Algorithm Using Hot-Electron Injection for Programming Analog Computational Memory Elements Within 0.2% of Accuracy Over 3.5 Decades

    Page(s): 2107 - 2114
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    This paper describes a new predictive algorithm that can be used for programming large arrays of analog computational memory elements within 0.2% of accuracy for 3.5 decades of currents. The average number of pulses required are 7-8 (20 mus each). This algorithm uses hot-electron injection for accurate programming and Fowler-Nordheim tunneling for global erase. This algorithm has been tested for programming 1024times16 and 96times16 floating-gate arrays in 0.25 mum and 0.5 mum n-well CMOS processes, respectively View full abstract»

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  • A 32-KB Standard CMOS Antifuse One-Time Programmable ROM Embedded in a 16-bit Microcontroller

    Page(s): 2115 - 2124
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    A 32-KB standard CMOS antifuse one-time programmable (OTP) ROM embedded in a 16-bit microcontroller as its program memory is designed and implemented in 0.18-mum standard CMOS technology. The proposed 32-KB OTP ROM cell array consists of 4.2 mum2 three-transistor (3T) OTP cells where each cell utilizes a thin gate-oxide antifuse, a high-voltage blocking transistor, and an access transistor, which are all compatible with standard CMOS process. In order for high density implementation, the size of the 3T cell has been reduced by 80% in comparison to previous work. The fabricated total chip size, including 32-KB OTP ROM, which can be programmed via external I 2C master device such as universal I2C serial EEPROM programmer, 16-bit microcontroller with 16-KB program SRAM and 8-KB data SRAM, peripheral circuits to interface other system building blocks, and bonding pads, is 9.9 mm2. This paper describes the cell, design, and implementation of high-density CMOS OTP ROM, and shows its promising possibilities in embedded applications View full abstract»

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  • Introduction to the Special Issue on the IEEE Bipolar/BiCMOS Circuits and Technology Meeting

    Page(s): 2125 - 2126
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    Freely Available from IEEE
  • Notice of Violation of IEEE Publication Principles
    A 12.5 Gb/s Electro-Absorption-Modulator Driver Using an Adaptive Compensated Push-Pull Emitter Follower and a Cascode Output Switch With Dynamic Headroom Allocation

    Page(s): 2127 - 2143
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    Notice of Violation of IEEE Publication Principles

    "A 12.5 Gb/s Electro-Absorption-Modulator Driver Using an Adaptive Compensated Push-Pull Emitter Follower and a Cascode Output Switch With Dynamic Headroom Allocation"
    by Maxim, A.
    in the IEEE Journal of Solid-State Circuits,
    Volume 41, Issue 9, Sept. 2006 Page(s):2127 - 2143

    After careful and considered review, it has been determined that the above paper is in violation of IEEE's Publication Principles.

    Specifically, the paper contains information that Adrian Maxim admits had been falsified. In response to an inquiry on this misconduct, Mr. Maxim acknowledged that the following people who have been listed as co-authors on several of his papers are fabricated names and that he is the only author:

    C. Turinici,D. Smith, S. Dupue

    Additionally, in papers by Mr. Maxim that have co-authors other than those listed above, it was discovered in some cases that he had not consulted with them while writing the papers, and submitted papers without their knowledge.

    Although Mr. Maxim maintains that not all of the data is falsified, IEEE nevertheless cannot assure the integrity of papers posted by him because of his repeated false statements.

    Due to the nature of this violation, reasonable effort should be made to remove all past references to the above paper, and to refrain from any future references.A 9.953-12.5 Gb/s EAM driver IC was realized in a 60 GHz fT 0.2 mum SOI SiGe HBT process. Fast switching was achieved by using a cascode output switch that minimizes the capacitive load on the pre-driver and also allows an on-chip summation of the bias and modulation currents without degrading the signal path bandwidth. Low voltage operation was achieved by generating the modulation current with a common-mode feedback loop. Dynamic biasing was used to optimally allocate the headroom voltage between the switch and its cascode devices over supply, temperature, bias- and modulation corners. An adaptive RC compensation that tracks the modulation current was implemented to cancel the inductive behavior of the last emitter follower stage. The EAM driver specifications include 20 to 120 mA modulation current range, 1 to 60 mA bias current range, <15 pspp deterministic jitter, <25 ps rise/fall time, plusmn80 ps pulse-width adjustment, 4.75 to 5.5 V supply voltage and 1.3times1.7 mm2 die area View full abstract»

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  • A 100-dB SFDR 80-MSPS 14-Bit 0.35-  \mu\hbox {m} BiCMOS Pipeline ADC

    Page(s): 2144 - 2153
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    This paper describes a 14-bit 80-MSPS ADC with 100-dB SFDR at 70-MHz input frequency in a 0.35-mum single-well BiCMOS technology drawing 1.2 W from a dual 3.3 V/5.0 V supply. Key barriers to high dynamic range in pipeline ADCs at high clock rates and some methods to overcome these barriers will be presented. These methods include a sampling front-end without the use of a designated Sample and Hold (S/H). A BiCMOS switching input buffer is used along with the strategic use of BiCMOS design techniques. Also, calibration is combined with capacitor shuffling to maximize linearity with minimal noise impact View full abstract»

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  • 2.5 V 43&#8211;45 Gb/s CDR Circuit and 55 Gb/s PRBS Generator in SiGe Using a Low-Voltage Logic Family

    Page(s): 2154 - 2165
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    An alternative design approach for implementing high-speed digital and mixed-signal circuits is proposed. It is based on a family of low-voltage logic gates with reduced transistor stacking compared to series-gated emitter-coupled logic. It includes a latch, an XOR gate, and a MUX with mutually compatible interfaces. Topologies and characteristics of the individual gates are discussed. Closed-form propagation delay expressions are introduced and verified with simulations. The proposed design style was used to implement a 43-45 Gb/s CDR circuit with a 600MHz locking range and a 55 Gb/s PRBS generator with a 27-1 sequence length. The circuits were fabricated in a SiGe BiCMOS technology with fT=120 GHz. Corresponding measurement results validate the proposed design style and establish it as a viable alternative to emitter-coupled logic in high-speed applications. Both circuits operate from a 2.5 V nominal power supply and consume 650 mW and 550 mW, respectively View full abstract»

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  • Adaptive Multi-Band Multi-Mode Power Amplifier Using Integrated Varactor-Based Tunable Matching Networks

    Page(s): 2166 - 2176
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    This paper presents a multi-band multi-mode class-AB power amplifier, which utilizes continuously tunable input and output matching networks integrated in a low-loss silicon-on-glass technology. The tunable matching networks make use of very high Q varactor diodes (Q>100 @ 2 GHz) in a low distortion anti-series configuration to achieve the desired source and load impedance tunability. A QUBIC4G (SiGe, ft=50 GHz) high voltage breakdown transistor (VCBO=14 V, VCEO>3.6 V) is used as active device. The realized adaptive amplifier provides 13 dB gain, 27-28 dBm output power at the 900, 1800, 1900 and 2100 MHz bands. For the communication bands above 1 GHz optimum load adaptation is facilitated resulting in efficiencies between 30%-55% over a 10 dB output power control range. The total chip area (including matching networks) of the amplifier is 8 mm2 View full abstract»

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  • A Low-Voltage Broadband Feedforward-Linearized BJT Mixer

    Page(s): 2177 - 2187
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    A low-voltage, feedforward-linearized bipolar mixer realizes an input IP3 of +14.3 dBm and an input IP2 of +54.5 dBm at 2.4 GHz. Conversion (power) gain over the 1-6GHz RF input range is 12.4plusmn0.35 dB, while the input IP3 is 13.6plusmn1.8dBm over the same frequency range. The broadband mixer's RF input impedance varies from 60.3-j7.1 at 2.4 GHz to 57.4-j16.6 Omega at 5.8GHz. Measured SSB (50 Omega) noise figure is 18.6 dB at 2.4 GHz. No on-chip inductors are used in the design, and the 0.14 mm 2 (active area) mixer dissipates 7.2 mW from a (minimum) 1.2 V supply View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Editor-in-Chief
Michael Flynn
University of Michigan