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Circuits, Devices and Systems, IEE Proceedings G

Issue 1 • Date Feb 1992

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Displaying Results 1 - 23 of 23
  • Silicon-on-sapphire MOSFET model for analogue circuit simulation

    Page(s): 33 - 36
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (260 KB)  

    A simple, physically based circuit simulation model for silicon-on-sapphire (SOS) MOSFETs is presented. The model has been implemented in SPICE and shows accurate prediction of the onset of the kink effect. Simulation results of amplifier circuits show significant improvement in predicting operating point and gain compared with bulk MOS models View full abstract»

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  • Rapid determination of long generation lifetime

    Page(s): 1 - 4
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (268 KB)  

    The determination of the long generation lifetime by using the Zerbst plot technique or the saturation capacitance technique are time-consuming. A new rapid technique suitable to determine the long generation lifetime is suggested. This method is based on analysing the non-saturation C-t transient of an MOS capacitor under a linear voltage sweep. A depletion linear voltage sweep at a relatively high rate will drive an MOS capacitor into a deep depletion state rapidly. As the capacitance-saturation need not be reached, drawing such a C-t transient curve is time-saving. A simple procedure may be used to extract the generation lifetime from this curve. The experiments show that the measured results are well self-consistent and the method is reasonable and appreciatively time-saving View full abstract»

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  • Adaptive learning circuit based on the Walsh transform

    Page(s): 23 - 26
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (236 KB)  

    A novel adaptive function learning circuit based on appropriately configured Walsh matrices and the Walsh transform compares favourably with artificial neural networks. A Walsh-vector generator produces parallel outputs corresponding to the circuit input. A single layer of weights connected to the Walsh-vector generator outputs is summed to produce the circuit output and is updated using a simple algorithm. Fast and reliable learning is obtained with the weights themselves converging towards the coefficients of the Walsh transform of the desired output function View full abstract»

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  • Electrical capacitance tomography for flow imaging: system model for development of image reconstruction algorithms and design of primary sensors

    Page(s): 89 - 98
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (740 KB)  

    A software tool that facilitates the development of image reconstruction algorithms, and the design of optimal capacitance sensors for a capacitance-based 12-electrode tomographic flow imaging system are described. The core of this software tool is the finite element (FE) model of the sensor, which is implemented in OCCAM-2 language and run on the Inmos T800 transputers. Using the system model, the in-depth study of the capacitance sensing fields and the generation of flow model data are made possible, which assists, in a systematic approach, the design of an improved image-reconstruction algorithm. This algorithm is implemented on a network of transputers to achieve a real-time performance. It is found that the selection of the geometric parameters of a 12-electrode sensor has significant effects on the sensitivity distributions of the capacitance fields and on the linearity of the capacitance data. As a consequence, the fidelity of the reconstructed images are affected. Optimal sensor designs can, therefore, be provided, by accommodating these effects View full abstract»

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  • Analogy between VLSI floorplanning problems and realisation of a resistive network

    Page(s): 99 - 103
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (332 KB)  

    The problem of minimising the area of a rectangular VLSI chip by a proper choice of dimensions of the rectangular blocks forming the chip is discussed. The layout of the chip is defined by its floorplan with the areas of the building blocks given a priori. An analogy is used which exists between this problem and the problem of designing a resistive network with a given topology. In such an analogy, the area of a block or the whole chip corresponds to the power absorbed in a resistor or the whole network, respectively. Since the total power absorbed by the network is equal to the sum of the power absorbed by the resistors, the network model inherently corresponds to a chip design with zero wasted area. Thus, in terms of the network realisation concepts, the problem reduces to finding assignment of resistor values to a network with a given topology such that the power absorbed in each of the resistors is given a priori. A step-by-step procedure is presented which shows a way to reach an approximate solution in a finite number of steps View full abstract»

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  • Crosstalk tolerant latch circuit

    Page(s): 5 - 8
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (208 KB)  

    The authors present a D-latch sequential circuit that exhibits an elevated degree of tolerance to common and differential mode noise in the clock lines. For these lines the noise tolerance overruns the power supply voltage (Vdd). In the fraction of the tolerance range with the highest level of noise the circuit becomes a dynamic latch preserving the circuit from the propagation of errors. The circuit and the design rules presented, are oriented to VLSI circuit design in which crosstalk interferences might be foreseen View full abstract»

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  • Fundamental limitations of switched-capacitor sigma-delta modulators

    Page(s): 27 - 32
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (452 KB)  

    In recent years oversampling techniques have become very popular for implementing high resolution analogue-to-digital (A/D) convertors. To obtain high resolution the order of the modulator L and the oversampling ratio M are commonly seen as degrees of freedom since no theoretical limit exists for the maximum achievable signal-to-quantisation-noise ratio (SNR). However, in practical cases two fundamental constraints need to be considered in the design of the modulator, namely the thermal noise generated by the switches and the amplifiers and the settling error due to finite values of the gain-bandwidth product and the slew rate. The authors present a closed form relation for the SNR performance of generic L-order N -bit modulators designed with switched-capacitor (SC) techniques. The relation takes into account all the above constraints. One of the major conclusions is that state-of-the-art 2nd-order SC modulators are sufficient to achieve competitive SNR performance View full abstract»

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  • Improved objective function for device model parameter extraction

    Page(s): 126 - 130
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (344 KB)  

    Curve-fitting is a reliable strategy for the automated extraction of the parameter set of an analytical device model from measured data. This strategy always implies the minimisation of a nonlinear objective function that comprises the differences between a set of measured data points and the model. A new type of objective function is proposed that is not based on the common concept of a division between dependent and independent terminal variables, but on a concept where all terminal variables are equally treated. This objective function, which is derived from the principle of maximum likelihood estimation, can be expressed as a sum of squares of nonlinear functions, so that the computationally efficient class of Gauss-Newton methods can be used for its optimisation. Results show that, for strongly nonlinear models in particular, the convergence properties are significantly improved View full abstract»

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  • Diakoptic and large change sensitivity analysis

    Page(s): 114 - 118
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (236 KB)  

    An approach to the analysis of large circuits based on the use of the large change sensitivity technique applied to decomposed networks is presented. As a result of this approach a simple, compact notation for the solution vector is derived. The method is applicable to nonlinear analogue networks with hierarchical decomposition simulated by inserted ideal switches. A simple illustrative example is given View full abstract»

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  • New synthesis techniques for high order all-pole filters

    Page(s): 9 - 16
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (580 KB)  

    A new method for partitioning a high order all-pole filter into an interconnection of subsystems is described. It was found that conventional all-cascade and all-parallel implementations were unsuitable and the theory of filter implementations is enhanced by appealing to polynomial theory. This theory is presented, prefaced by a description of the context in which the work was done, and followed by some examples. It is shown that, for high order models, the filter coefficients exhibit far less variation between maximum and minimum absolute values, making them more practical to implement View full abstract»

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  • Design of sensor electronics for electrical capacitance tomography

    Page(s): 83 - 88
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (460 KB)  

    The design of the sensor electronics for a tomographic imaging system based on electrical capacitance sensors is described. The performance of the sensor electronics is crucial to the performance of the imaging system. The problems associated with such a measurement process are discussed and solutions to these are described. Test results show that the present design has a resolution of 0.3 femtofarad. (For a 12-electrode system imaging an oil/gas flow, this represents a 2% gas void fraction change at the centre of the pipe) with a low noise level of 0.08 fF (RMS value), a large dynamic range of 76 dB and a data acquisition speed of 6600 measurements per second. This enables sensors with up to 12 electrodes to be used in a system with a maximum imaging rate of 100 frames per second, and thus provides an improved image resolution over the earlier 8-electrode system and an adequate electrode area to give sufficient measurement sensitivity View full abstract»

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  • Analysis and simulation of automatic bias reduction circuit in a coherent detector

    Page(s): 57 - 62
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (264 KB)  

    The circuit analysis and performance simulation of the auto zero circuit (AZC) of a coherent detector are presented. Also the characteristics of the auto zero circuit in such a detector are investigated. Computer simulation verifies that the convergence time of the residual bias is inversely proportional to the amplitude of the gain in the auto zero circuit, and the residual bias of the coherent detector is proportional to the amplitude of the gain. For a specified receiver noise power and the tolerable residual bias of the coherent detector, the required parameters of an auto zero circuit can be selected using the results developed in the paper View full abstract»

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  • Bit-sliced median filter design based on majority gate

    Page(s): 63 - 71
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (572 KB)  

    There are arithmetic problems for the hardware realisation of bit-level median filtering algorithms. The design of a majority gate which is composed of output-wired inverters is proposed. The area and time complexities are better than the digital and analogue designs now available. This circuit is applied to a median filter design which is based on majority selection, the computation problems are thus avoided. It is a bit-sliced architecture with constant cycle time. Window shapes can be arbitrarily changed through mask-and-set modules. A median filtering system for two-dimensional image processing is presented View full abstract»

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  • Tomographic imaging of industrial process equipment: techniques and applications

    Page(s): 72 - 82
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (868 KB)  

    Opportunities for the use of noninvasive tomographic sensor technology are described and reviewed critically. Imaging instruments based on electrical sensing methods are discussed with respect to a number of process applications, including measurement of component concentration profiles, phase boundaries, component velocities and component mass flow rate. The use of low-noise electronic devices for process image sensing and the computationally intensive digital signal processing systems for image reconstruction are discussed. Limitations of current electronic techniques, particularly for future ultra high speed image reconstruction are revealed and directions for future progress are elucidated View full abstract»

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  • Modelling and setting times of amplifiers in SC circuits

    Page(s): 131 - 135
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (332 KB)  

    Various types of amplifier used in SC circuits are modelled and compared by studying their settling behaviour when they are embedded in a capacitive environment. It is shown that the frequently used buffered op-amp model does not coincide with the amplifiers used in practical SC circuits. The comparison of single and two stage amplifiers shows definite advantages in the former especially when built as cascode OTAs. Formulas for the performance under slew rate conditions are also developed. Lastly, simulated frequency responses using the two amplifiers with high clock rates are reported View full abstract»

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  • Modelling and test generation for MOS transmission gate stuck-open faults

    Page(s): 17 - 22
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (348 KB)  

    The authors present a testable design for a MOS transmission gate (whether it is a pass transistor or a CMOS transmission gate) when it is isolated (i.e. it does not have transmission gate neighbours nor does it feed a bus) and subject to a stuck-open fault condition in a given CMOS VLSI circuit. The proposed design consists of the original transmission gate to which a MOS transistor is added, so that the high impedance state resulting from a stuck-open fault condition can be eliminated. It is shown that the new approach can be extended to MOS transmission gate-based multiplexers for which a better testing scheme is ensured. It is also demonstrated that not all transmission gates need to be augmented by using an additional MOS transistor, so that the circuit under study can be kept combinational while in the test mode. Finally, the test generation for isolated transmission gates in the context of the PODEM algorithm is discussed View full abstract»

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  • High-performance bit-serial adders and multipliers

    Page(s): 109 - 113
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (372 KB)  

    A design methodology is presented which uses clocked logic modules to synthesise flexible high performance multipliers. By using two-stage pipelined bit-serial adders, a bit-serial multiplier can be designed which is capable of producing both single- and double-precision products for continuous two's complement data streams. High processing speeds are possible owing to the systolic structure which is pipelined at the gate level View full abstract»

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  • Study and characterisation of MOSFET integrated magnetodetector based on hot carrier detection

    Page(s): 119 - 125
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (416 KB)  

    An experimental study and analytical modelling of a novel MOSFET integrated magnetodetector are presented. It is based on the injection of hot electrons from a MOSFET channel into a split floating gate. The magnetic field to be measured deviates the hot carrier stream in the floating gate towards one of the two gate splits. These splits feed the input of a very low level current to frequency convertor. A linear response (better than 2%) over a very wide range of measurement (106) to the magnetic field is experimentally demonstrated. A very high sensitivity (10 nT) is also measured. The high sensitivity and wide range of measurement are attributed to a new leakage compensation technique and to an exponential conversion of the magnetic current into frequency View full abstract»

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  • Low temperature behaviour of channel transit time constant in MOS transistor

    Page(s): 104 - 108
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (264 KB)  

    The channel transient response time constant of a MOS transistor is studied through the transmission line network of the conductance channel in the 296-77 K temperature range. The temperature dependence of the channel transit time constant is modelled through the temperature sensitive parameters such as inversion layer mobility, the Fermi potential, intrinsic carrier concentration and threshold voltage. It is shown that the channel time constant is strongly sensitive to the temperature variation in the inversion region and results in the MOS transistor channel resistance having zero, negative and positive temperature coefficients depending upon the gate bias voltage View full abstract»

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  • Residual phase noise performance of X-band GaAs FET amplifiers at liquid nitrogen temperature

    Page(s): 37 - 38
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (132 KB)  

    High-performance X-band GaAs FET amplifiers were evaluated at room temperature and 77 K, to determine the residual phase noise of the amplifiers. The data revealed 15-50 dBc/Hz degradation in the close-in residual phase noise when the amplifiers were operated at 77 K View full abstract»

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  • Tellegen theorem and modelling of power systems-PV buses and nonlinear formulas

    Page(s): 136 - 140
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (276 KB)  

    Tellegen's theorem has often been used to derive network sensitivities for a variety of systems, including power systems. Recently, Tellegen's theorem has been used to derive approximate nonlinear formulas for evaluating the response of a power system to large network perturbations. Those formulas are efficient and yield accurate results, but the efficiency deteriorates dramatically for systems with PV buses. The reason for the deterioration is that the coefficients of the formulas are computed under the assumption of PQ buses; hence, the resulting formulas have to be iteratively corrected. In the paper, approximate noniterative nonlinear formulas are developed which include PV and PQ buses with equal ease. The modelling behind these formulas is presented. It is shown that, whereas a PQ bus leads to a voltage controlled current source, a PV bus leads to a current controlled voltage source. It is also shown that the corresponding adjoint solutions can be obtained by solving a system of linear equations. A complete numerical example is provided to enable the replication of the results View full abstract»

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  • Reduced-order models of 2-D linear discrete separable-denominator system using bilinear Routh approximations

    Page(s): 45 - 56
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (672 KB)  

    The authors extend the Routh approximation method for one-dimensional (1-D) discrete systems to two-dimensional (2-D) discrete systems for finding stable reduced-order models from a stable high-order 2-D linear discrete separable-denominator system (SDS). The extension is achieved by exploring new properties of the 1-D Routh canonical model and establishing new 2-D bilinear Routh canonical models. Without explicitly performing bilinear transformations, a computationally-efficient procedure is presented for finding the bilinear Routh reduced-order models. The properties of the obtained 2-D bilinear Routh approximants are discussed in detail. In addition, a new 2-D bilinear Routh canonical state-space realisation is presented from which the low-dimensional state-space models corresponding to the bilinear Routh approximants can be obtained by a direct truncation procedure. Furthermore, the relationships among the states of the bilinear Routh reduced-dimension model, the aggregated model, and the original system are explored. Numerical examples are given to demonstrate the effectiveness of the proposed method View full abstract»

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  • Adaptive quantisation for one-bit sigma-delta modulation

    Page(s): 39 - 44
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (376 KB)  

    A fixed step size is usually used for a quantiser in a sigma-delta modulator or noise shaper, but it cannot always match input signals adequately if they are nonstationary, as in the case of music. An attempt at introducing adaptive quantisers, based on a digital maximum-magnitude technique, into 1-bit sigma-delta modulators has been made, although the basic idea appeared about two decades ago. The initial results show it to be a promising technique. The dynamic range of the sigma-delta modulator can be effectively increased by using an adaptive quantiser, and the signal/noise ratio is nearly independent of input level for sinewave inputs. This advantage may increase future applications of sigma-delta modulators View full abstract»

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