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# IEEE Transactions on Electron Devices

## Filter Results

Displaying Results 1 - 25 of 67
• ### [Front cover]

Publication Year: 2006, Page(s): c1
| PDF (78 KB)
• ### IEEE Transactions on Electron Devices publication information

Publication Year: 2006, Page(s): c2
| PDF (60 KB)

Publication Year: 2006, Page(s):1953 - 1955
| PDF (72 KB)
• ### Blank page

Publication Year: 2006, Page(s): 1956
| PDF (2 KB)
• ### Special Issue on Advanced Compact Models and 45-nm Modeling Challenges

Publication Year: 2006, Page(s):1957 - 1960
| PDF (152 KB) | HTML
• ### Characteristics and Modeling of Sub-10-nm Planar Bulk CMOS Devices Fabricated by Lateral Source/Drain Junction Control

Publication Year: 2006, Page(s):1961 - 1970
Cited by:  Papers (13)
| | PDF (596 KB) | HTML

Sub-10-nm planar bulk CMOS devices were demonstrated by a lateral source/drain (S/D) junction control, which consists of the notched gate electrode, shallow S/D extensions, and steep halo in a reverse-order S/D formation. Furthermore, the transport properties were also evaluated by using those sub-10-nm planar bulk MOSFETs. The direct-tunneling currents between the S/D regions, with not only the g... View full abstract»

• ### Modeling Advanced FET Technology in a Compact Model

Publication Year: 2006, Page(s):1971 - 1978
Cited by:  Papers (40)
| | PDF (477 KB) | HTML

The need for meeting the expectations of continuing the enhancement of CMOS performance and density has inspired the introduction of new materials into the classical single-gate bulk MOSFET and the development of nonclassical multigate transistors at an accelerated rate. There is a strong need to understand and model the associated new physics and electrical behavior to ensure widespread very-larg... View full abstract»

• ### PSP: An Advanced Surface-Potential-Based MOSFET Model for Circuit Simulation

Publication Year: 2006, Page(s):1979 - 1993
Cited by:  Papers (188)  |  Patents (1)
| | PDF (618 KB) | HTML

This paper describes the latest and most advanced surface-potential-based model jointly developed by The Pennsylvania State University and Philips. Specific topics include model structure, mobility and velocity saturation description, further development and verification of symmetric linearization method, recent advances in the computational techniques for the surface potential, modeling of gate t... View full abstract»

• ### HiSIM2: Advanced MOSFET Model Valid for RF Circuit Simulation

Publication Year: 2006, Page(s):1994 - 2007
Cited by:  Papers (60)  |  Patents (3)
| | PDF (803 KB) | HTML

The compact MOSFET model development trend leads to models based on the channel surface potential, allowing higher accuracy and a reduced number of model parameters. Among these, the Hiroshima University Semiconductor Technology Academic Research Center IGFET Model (HiSIM) solves the surface potentials with an efficient physically correct iteration procedure, thus avoiding additional approximation... View full abstract»

• ### A Physics-Based Analytic Solution to the MOSFET Surface Potential From Accumulation to Strong-Inversion Region

Publication Year: 2006, Page(s):2008 - 2016
Cited by:  Papers (36)
| | PDF (413 KB) | HTML

A physics-based analytic solution to the surface potential from the accumulation to the strong-inversion region has been derived from the complete MOSFET surface potential equation in this paper without any need for smooth functions or simplification by dropping some second-order related terms. Its high accuracy in predicting the surface potential and the transcapacitance under various bias condit... View full abstract»

• ### Completely Surface-Potential-Based Compact Model of the Fully Depleted SOI-MOSFET Including Short-Channel Effects

Publication Year: 2006, Page(s):2017 - 2024
Cited by:  Papers (33)  |  Patents (3)
| | PDF (366 KB) | HTML

The reported circuit simulation model Hiroshima University semiconductor technology academic research center IGFET model silicon-on-insulator (HiSIM-SOI) for the fully depleted SOI-MOSFET is based on a complete surface-potential description. Not only the surface potential in the MOSFET channel, but also the potentials at both surfaces of the buried oxide are solved iteratively, which allows includ... View full abstract»

• ### A Carrier-Transit-Delay-Based Nonquasi-Static MOSFET Model for Circuit Simulation and Its Application to Harmonic Distortion Analysis

Publication Year: 2006, Page(s):2025 - 2034
Cited by:  Papers (26)
| | PDF (516 KB) | HTML

In this paper, a compact model of nonquasi-static (NQS) carrier-transport effects in MOSFETs is reported, which takes into account the carrier-response delay to form the channel. The NQS model, as implemented in the surface-potential-based MOSFET Hiroshima University STARC IGFET model, is verified to predict the correct transient terminal currents and to achieve a stable circuit simulation. Simula... View full abstract»

• ### A Unified Nonquasi-Static MOSFET Model for Large-Signal and Small-Signal Simulations

Publication Year: 2006, Page(s):2035 - 2043
Cited by:  Papers (19)
| | PDF (293 KB) | HTML

The spline collocation-based nonquasi-static (NQS) model is further developed to include all regions of operation and small-geometry effects. The new formulation provides a unified (hence consistent) approach to both large-signal and small-signal NQS modeling and is sufficiently flexible to work with any surface-potential-based MOSFET model. The model is verified through comparison with the channe... View full abstract»

• ### Compact Modeling of Anomalous High-Frequency Behavior of MOSFET's Small-Signal NQS Parameters in Presence of Velocity Saturation

Publication Year: 2006, Page(s):2044 - 2050
Cited by:  Papers (4)
| | PDF (200 KB) | HTML

This paper presents a physical charge-based compact small-signal nonquasi-static (NQS) model for MOST, including velocity saturation and valid in all regions of inversion (from weak to strong inversion). This model intrinsically predicts the anomalous high-frequency behavior of transadmittance (ydg) in saturation, which was observed earlier in both device simulation and measurement. It ... View full abstract»

• ### Compact Noise Models for MOSFETs

Publication Year: 2006, Page(s):2051 - 2061
Cited by:  Papers (57)
| | PDF (421 KB) | HTML

A physical understanding of both intrinsic and extrinsic noise mechanisms in a MOSFET is developed. Intrinsic noise mechanisms fundamental to device operation include channel thermal noise, induced gate noise, and induced substrate noise. While the effect of channel thermal noise is observable at zero drain-to-source voltage, the induced gate and substrate noise do not manifest themselves under th... View full abstract»

• ### High-Frequency Noise of Modern MOSFETs: Compact Modeling and Measurement Issues

Publication Year: 2006, Page(s):2062 - 2081
Cited by:  Papers (79)  |  Patents (1)
| | PDF (1655 KB) | HTML

Compact modeling of the most important high-frequency (HF) noise sources of the MOSFET is presented in this paper, along with challenges in noise measurement and deembedding of future CMOS technologies. Several channel thermal noise models are reviewed and their ability to predict the channel noise of extremely small devices is discussed. The impact of technology scaling on noise performance of MO... View full abstract»

• ### An Analytic Model to Account for Quantum&#8211;Mechanical Effects of MOSFETs Using a Parabolic Potential Well Approximation

Publication Year: 2006, Page(s):2082 - 2090
Cited by:  Papers (10)
| | PDF (750 KB) | HTML

An analytic model to account for the quantum-mechanical effects (QMEs) of the MOSFETs using a parabolic potential well approximation is presented in this paper. Based on the solution of the coupled Schroumldinger and Poisson equations following the Wentzel-Kramer-Brillouin method, a transcendental equation of the subband energy level has been rigorously derived to obtain an approximate analytic so... View full abstract»

• ### Analytical Modeling of Output Conductance in Long-Channel Halo-Doped MOSFETs

Publication Year: 2006, Page(s):2091 - 2097
Cited by:  Papers (10)
| | PDF (352 KB) | HTML

In this paper, a detailed physical analysis and an analytical derivation of the degradation of the output resistance (Rout) observed in relatively long-channel laterally nonuniformly doped devices with halo implants are presented. Two-dimensional device simulations were performed, and the simulations show that the channel can be split into two uniformly doped transistors in series for t... View full abstract»

• ### The Physical Background of JUNCAP2

Publication Year: 2006, Page(s):2098 - 2107
Cited by:  Papers (19)
| | PDF (452 KB) | HTML

A new physics-based junction model for CMOS, called JUNCAP2, is presented. It contains new single-piece formulations for the Shockley-Read-Hall generation/recombination current and the trap-assisted tunneling (TAT) current, which are valid both in forward and reverse mode of operation. Moreover, the TAT model extends the existing model (IEEE Trans. Electron Devices, vol. 39, p. 2090, 1992) to the ... View full abstract»

• ### MOSFET ESD Breakdown Modeling and Parameter Extraction in Advanced CMOS Technologies

Publication Year: 2006, Page(s):2108 - 2117
Cited by:  Papers (3)  |  Patents (2)
| | PDF (341 KB) | HTML

This paper describes an approach for modeling the breakdown and snapback behavior of state-of-the-art MOSFET structures using equivalent-circuit description. Such models are required to enable circuit-level electrostatic discharge reliability simulations, which are a major challenge for the industry nowadays. Special attention is given to accurately describing the junction and gate leakage current... View full abstract»

• ### A Program for Device Model Parameter Extraction from Gate Capacitance and Current of Ultrathin$hboxSiO_2$and High-$kappa$Gate Stacks

Publication Year: 2006, Page(s):2118 - 2127
Cited by:  Papers (4)
| | PDF (646 KB) | HTML

A modeling tool is demonstrated for fast and automatic gate dielectric characterization and parameter extraction for the 45-nm CMOS technology node and beyond. The model incorporates a nonlinear least squares fitting program with the ability to extract nanometer-scale equivalent oxide thicknesses (EOTs) SiO2 and high-dielectric-constant (high-kappa) gate dielectrics from experimental ga... View full abstract»

• ### Compact-Modeling Solutions For Nanoscale Double-Gate and Gate-All-Around MOSFETs

Publication Year: 2006, Page(s):2128 - 2142
Cited by:  Papers (63)
| | PDF (616 KB) | HTML

Compact-modeling principles and solutions for nanoscale double-gate and gate-all-around MOSFETs are explained. The main challenges of compact modeling for these devices are addressed, and different approaches for describing the electrostatics, the transport mechanisms, and the high-frequency behavior are explained. Several approximations used to derive analytical solutions of Poisson's equation fo... View full abstract»

• ### Modeling and Significance of Fringe Capacitance in Nonclassical CMOS Devices With Gate&#8211;Source/Drain Underlap

Publication Year: 2006, Page(s):2143 - 2150
Cited by:  Papers (51)  |  Patents (2)
| | PDF (619 KB) | HTML

Parasitic gate-source/drain (G-S/D) fringe capacitance in nonclassical nanoscale CMOS devices, e.g., double-gate (DG) MOSFETs, is shown, using two-dimensional numerical simulations, to be very significant, gate bias-dependent, and substantially reduced by a well-designed G-S/D underlap. Analytical modeling of the outer and inner components of the fringe capacitance is developed and verified by the... View full abstract»

• ### A Compact Physical Model for Yield Under Gate Length and Body Thickness Variations in Nanoscale Double-Gate CMOS

Publication Year: 2006, Page(s):2151 - 2159
Cited by:  Papers (17)
| | PDF (513 KB) | HTML

Double-gate (DG) CMOS is projected to replace classical bulk and silicon-on-insulator technologies around the 32-nm node. Predicting the impact of process variations on yield for these devices is necessary at an early stage of the design cycle to enable optimal technology and circuit design choices. This paper presents a compact physical model for DG leakage and threshold voltage distribution due ... View full abstract»

• ### Impact of Scaling on Analog Performance and Associated Modeling Needs

Publication Year: 2006, Page(s):2160 - 2167
Cited by:  Papers (53)
| | PDF (334 KB) | HTML

This paper explores modeling and technology-scaling issues related to analog performance in advanced CMOS technologies. Performance metrics for analog circuits are defined, to provide insight into the impact of device scaling on power-constrained analog circuit design. Current and previous generation technologies (90 nm and older) are evaluated using standard compact models. Technology nodes below... View full abstract»

## Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Giovanni Ghione
Politecnico di Torino,
10129 Torino, Italy