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IEEE Transactions on Computers

Issue 7 • Date July 1987

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Displaying Results 1 - 18 of 18
  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1987, Page(s): c1
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  • IEEE Computer Society

    Publication Year: 1987, Page(s): c2
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  • Optimization Models for Configuring Distributed Computer Systems

    Publication Year: 1987, Page(s):773 - 793
    Cited by:  Papers (13)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (5170 KB)

    This paper develops models for designing the architecture of distributed computing systems of the type used to support corporate management and control activities. The data for the design process consist of two major data sets describing the inputs and outputs to the information system and the relationships between them. The model accepts a listing of the relevant data sources in the organization,... View full abstract»

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  • A New Interconnection Network for SIMD Computers: The Sigma Network

    Publication Year: 1987, Page(s):794 - 801
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2251 KB)

    When processing vectors on SIMD computers, some data manipulations (rearrangement, expansion, compression, perfect-shuffle, bit-reversal) have to be performed by an interconnection network. When this network lacks an efficient routing control, it becomes the bottleneck for performance. It has been pointed out that general algorithms to control rearrangeable networks for arbitrary permutations are ... View full abstract»

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  • Programming Cellular Permutation Networks Through Decomposition of Symmetric Groups

    Publication Year: 1987, Page(s):802 - 809
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2455 KB)

    A fundamental problem in interconnection network theory is to design permutation networks with as few cells as possible and a small programming or setup time. The well-known networks of Benes and Waksman have asymptotically optimal cell counts, but the best setup algorithm available for such networks with n inputs requires O(n log2 n) sequential time. As an alternative, this paper considers anothe... View full abstract»

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  • On the Permutation Capability of Multistage Interconnection Networks

    Publication Year: 1987, Page(s):810 - 822
    Cited by:  Papers (44)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3481 KB)

    We present analytic models for the blocking probability of both unique path and multiple path multistage interconnection networks under the assumption of either permutation or random memory request patterns. The blocking probability of an interconnection network under the assumption of permutation requests is a quantitative measure of the network's permutation capability. We compare the performanc... View full abstract»

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  • Analysis and Synthesis of Dynamic Multicomputer Networks that Reconfigure into Rings, Trees, and Stars

    Publication Year: 1987, Page(s):823 - 844
    Cited by:  Papers (9)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4612 KB)

    This paper presents analysis and synthesis techniques for multicomputer networks that perform fast reconfiguration into rings, stars, and trees. Each reconfiguration into a new network structure requires only two codes (reconfiguration code RC and bias B), and can be performed during one clock period. Because the reconfiguration methodology presented is based on some fine mathematical properties e... View full abstract»

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  • Stencils and Problem Partitionings: Their Influence on the Performance of Multiple Processor Systems

    Publication Year: 1987, Page(s):845 - 858
    Cited by:  Papers (40)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3672 KB)

    Given a discretization stencil, partitioning the problem domain is an important first step for the efficient solution of partial differential equations on multiple processor systems. We derive partitions that minimize interprocessor communication when the number of processors is known a priori and each domain partition is assigned to a different processor. Our partitioning technique uses the stenc... View full abstract»

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  • Characterization of Branch and Data Dependencies in Programs for Evaluating Pipeline Performance

    Publication Year: 1987, Page(s):859 - 875
    Cited by:  Papers (19)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4605 KB)

    The nature by which branches and data dependencies generate delays that degrade pipeline performance is investigated in this paper. We show that for the general execution trace, few specific delays can be considered in isolation; rather, the magnitude of any specific delay may depend on the relative proximity of other delays. This phenomenon can make the task of accurately characterizing a trace t... View full abstract»

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  • A Multiprocessor Architecture for Two-Dimensional Digital Filters

    Publication Year: 1987, Page(s):876 - 884
    Cited by:  Papers (33)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2580 KB)

    In this paper, a generic computational primitive is developed for the implementation of any arbitrary order one-dimensional or two-dimensional FIR or IIR digital filter. This computational primitive can form the basis for a single chip processor for one-dimensional and two-dimensional digital signal processing. A multiprocessor architecture for real-time implementation of spatial domain filters is... View full abstract»

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  • On Group Graphs and Their Fault Tolerance

    Publication Year: 1987, Page(s):885 - 888
    Cited by:  Papers (37)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (864 KB)

    This paper investigates group graphs as a source of interconnection networks. It is shown that while these graphs possess many properties desirable in all interconnection networks, their diversity allows the generation of interconnection networks which may be optimized with regard to a variety of specific parameters. Techniques are described for generating, combining, and analyzing these graphs wi... View full abstract»

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  • Assignment of Job Modules onto Array Processors

    Publication Year: 1987, Page(s):888 - 891
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (796 KB)

    This paper deals with the optimum assignment of job modules onto array processors. In array processors it is important to assign job modules onto processors such that the modules that communicate with each other are assigned to adjacent processors, because communication overhead increases as communications occur between processors that are remotely connected. We propose an efficient algorithm to s... View full abstract»

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  • A Minimum Test Set for Multiple Fault Detection in Ripple Carry Adders

    Publication Year: 1987, Page(s):891 - 895
    Cited by:  Papers (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1205 KB)

    Previous papers have shown that a ripple carry adder composed of several full adder cells can be completely tested by a minimum test set of size 8 independent of the number of cells in the ripple carry adder under single faulty cell assumption. The fault model assumed is that faults in a cell can change the cell behavior in any arbitrary way, as long as the cell remains a combinational circuit. In... View full abstract»

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  • On-the-Fly Conversion of Redundant into Conventional Representations

    Publication Year: 1987, Page(s):895 - 897
    Cited by:  Papers (159)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (484 KB)

    An algorithm to convert redundant number representations into conventional representations is presented. The algorithm is performed concurrently with the digit-by-digit generation of redundant forms by schemes such as SRT division. It has a step delay roughly equivalent to the delay of a carry-save adder and simple implementation. The conversion scheme is applicable in arithmetic algorithms such a... View full abstract»

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  • Editorials - from 1978

    Publication Year: 1987, Page(s): 898
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  • IEEE copyright form

    Publication Year: 1987, Page(s): 899
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  • IEEE Computer Society Publications

    Publication Year: 1987, Page(s): 899
    Request permission for commercial reuse | PDF file iconPDF (183 KB)
    Freely Available from IEEE
  • Information for authors

    Publication Year: 1987, Page(s): 899
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org