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IEEE Transactions on Computers

Issue 5 • May 1987

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Displaying Results 1 - 21 of 21
  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1987, Page(s): c1
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  • IEEE Computer Society

    Publication Year: 1987, Page(s): c2
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  • On Distributed Computations with Limited Resources

    Publication Year: 1987, Page(s):517 - 528
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3395 KB)

    We consider two styles of executing a single job or an algorithm: either the job is subdivided into tasks, each of which is executed. on a separate processor, or the entire job is executed on a single processor, that has the same capacity as the sum of the processors in the earlier case. The algorithm is abstracted as consisting of a number of tasks with dependencies among them. Our model of depen... View full abstract»

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  • Measurement-Based Analysis of Error Latency

    Publication Year: 1987, Page(s):529 - 537
    Cited by:  Papers (36)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2789 KB)

    This paper demonstrates a practical methodology for the study of error latency under a real workload. The method is illustrated with sampled data on the physical memory activity, gathered by hardware instrumentation on a VAX 11/780 during the normal workload cycle of the installation. These data are used to simulate fault occurrence and to reconstruct the error discovery process in the system. The... View full abstract»

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  • A Generalized Theory for System Level Diagnosis

    Publication Year: 1987, Page(s):538 - 546
    Cited by:  Papers (75)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3047 KB)

    System-level diagnosis appears to be a viable alternative to circuit-level testing in complex multiprocessor systems. A completely new generalization of the characterization problem in the system-level diagnosis area is developed in this paper. This generalized characterization theorem provides necessary and sufficient conditions for any fault-pattern of any size to be uniquely diagnosable, under ... View full abstract»

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  • Deadlock-Free Message Routing in Multiprocessor Interconnection Networks

    Publication Year: 1987, Page(s):547 - 553
    Cited by:  Papers (1153)  |  Patents (81)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2625 KB)

    A deadlock-free routing algorithm can be generated for arbitrary interconnection networks using the concept of virtual channels. A necessary and sufficient condition for deadlock-free routing is the absence of cycles in a channel dependency graph. Given an arbitrary network and a routing function, the cycles of the channel dependency graph can be removed by splitting physical channels into groups ... View full abstract»

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  • Modeling a Slotted Ring Local Area Network

    Publication Year: 1987, Page(s):554 - 561
    Cited by:  Papers (19)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2259 KB)

    Models for local area networks of the slotted ring style of architecture are developed and evaluated. The hardware protocol is modeled using a BCMP network. The Basic Block protocol of the Cambridge ring is modeled using an approximate solution method of the fixed-point type. A limited comparison between the Cambridge Ring and another ring architecture—the token ring—is carried out. View full abstract»

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  • A Scheduling-Function-Based Distributed Access Protocol that Uses CDM to Relay Control Information in a Network with Hidden Nodes

    Publication Year: 1987, Page(s):562 - 569
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2707 KB)

    We introduce a method for broadcasting control information (such as the information essential for correct operation of SOSAM and other scheduling-function-based access protocols) in stationary networks with "hidden" nodes (multihop networks). Control information is transmitted as short bit- parallel control messages on a separate control channel whose capacity is shared among the bits of a control... View full abstract»

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  • A Partitioning Strategy for Nonuniform Problems on Multiprocessors

    Publication Year: 1987, Page(s):570 - 580
    Cited by:  Papers (262)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (5307 KB)

    We consider the partitioning of a problem on a domain with unequal work estimates in different subdomains in a way that balances the workload across multiple processors. Such a problem arises for example in solving partial differential equations using an adaptive method that places extra grid points in certain subregions of the domain. We use a binary decomposition of the domain to partition it in... View full abstract»

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  • Parallelization and Performance Analysis of the Cooley–Tukey FFT Algorithm for Shared-Memory Architectures

    Publication Year: 1987, Page(s):581 - 591
    Cited by:  Papers (34)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3339 KB)

    We present here a study of parallelization of the Cooley-Tukey radix two FFT algorithm for MIMD (nonvector) architectures. Parallel algorithms are presented for one and multidimensional Fourier transforms. From instruction traces obtained by executing Fortran kernels derived from our algorithms, we determined the precise instructions to be executed by each processor in the parallel system. We used... View full abstract»

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  • Fault Propagation Through Embedded Multiport Memories

    Publication Year: 1987, Page(s):592 - 602
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3196 KB)

    An analytical method is described for determining the random pattern testability of permanent faults in the prelogic driving the data-in and the address lines of a multiport random access memory whose outputs are directly observable. The results can be used with minimal extensions to existing detection probability tools such as the cutting algorithm. View full abstract»

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  • Optimal Systolic Design for the Transitive Closure and the Shortest Path Problems

    Publication Year: 1987, Page(s):603 - 614
    Cited by:  Papers (70)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3313 KB)

    Due to VLSI technological progress, algorithm- oriented array architectures, such as systolic arrays, appear to be very effective, feasible, and economic. This paper discusses how to design systolic arrays for the transitive closure and the shortest path problems. We shall focus on the Warshall algorithm for the transitive closure problem and the Floyd algorithm for the shortest path problem. Thes... View full abstract»

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  • Complexity of Matrix Product on a Class of Orthogonally Connected Systolic Arrays

    Publication Year: 1987, Page(s):615 - 619
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (898 KB)

    This correspondence studies the time complexity of the parallel computation of the product C = A.B of two dense square matrices A, B of order n, on a class of rectangular orthogonally connected systolic arrays, which are the two-dimensional extensions of the classical pipeline scheme. Such arrays are composed of multiply-add cells without local memory, and, as C is computed, the coefficients cij m... View full abstract»

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  • On an Optimally Fault-Tolerant Multiprocessor Network Architecture

    Publication Year: 1987, Page(s):619 - 623
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1127 KB)

    This correspondence presents a class of optimally fault tolerant multiprocessor network architecture, based on the networks proposed earlier by Pradhan [71, where the networks are represented by regular digraphs. Because of optimal fault tolerapce, the number of connections per node is precisely related to the degree of fault tolerance the network is designed to provide. The routing of messgges in... View full abstract»

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  • General Criterion for Essential Nonfault Locatability of Logical Functions

    Publication Year: 1987, Page(s):623 - 629
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1843 KB)

    This correspondence presents a solution of a well-known essential problem of diagnostics open till now. The method of solution is based on a straight application of mathematical structures theory 1121, [11]and on a topological representation of Boolean algebras [ 1]l[1] [ 41] The principle idea of this approach is as follows. The distribution of diagnostic information is controlled in Boolean comb... View full abstract»

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  • Design of Fast Self-Testing Checkers for a Class of Berger Codes

    Publication Year: 1987, Page(s):629 - 634
    Cited by:  Papers (32)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1207 KB)

    The Berger codes are optimal separable codes that detect all undirectional errors. In this correspondence a new procedure of designing self-testing checkers (STC's) for codes with I information bits, where I = {2K-2, 2K-l} and I ≥ 3, is proposed. I ≥ 3. The new checker is basically composed of u = ⌈(I + 1)/2⌉ STC's for m-out-of-n codes with n = I + 1 a... View full abstract»

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  • A Solution to the Polynomial Hensel Code Conversion Problem

    Publication Year: 1987, Page(s):634 - 637
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (864 KB)

    The polynomial Hensel code of a rational function a(x)/ b(x) ϵ F(x), F is a field, is the pair (c(x) d-1(x) mod Xr, n); r is a positive integer and a(x)/ b(x) = (c(x))xn such that c(x) and d(x) have nonzero constant terms. Such a representation scheme was proposed, in analogy with the Hensel code representations of rational numbers, to facilitate arithmetic operations on rational functions a... View full abstract»

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  • Fault-Tolerant Single-Stage Interconnectiohl Networks

    Publication Year: 1987, Page(s):637 - 640
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (913 KB)

    Single-stage Beta interconnection networks have been proposed for connecting processing elements in multiprocessing systems. An efficient data routing strategy has been designed. Faulty switching elements in the network can be automatically diagnosed. Its fault-tolerant capability is achieved by allowing data to recirculate the network several more passes with the presence of faults. Two parameter... View full abstract»

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  • Integer Division in Linear Time with Bounded Fan-In

    Publication Year: 1987, Page(s):640 - 644
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (785 KB)

    A binary algorithm for division of an (M + N)-bit integer by an N-bit integer is presented. The algorithm produces the (M + 1)-bit quotient and the N-bit remainder in time O(M + N). Two hardware implementations, one using combinational logic in cellular arrays, and one employing systolic arrays, are given. These implementations are designed for modularity and regularity, and thus are suitable for ... View full abstract»

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  • IEEE Computer Society Publications

    Publication Year: 1987, Page(s): 644
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    Freely Available from IEEE
  • Information for authors

    Publication Year: 1987, Page(s): 644
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    Freely Available from IEEE

Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org