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IEEE Transactions on Computers

Issue 3 • March 1987

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Displaying Results 1 - 21 of 21
  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1987, Page(s): c1
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    Freely Available from IEEE
  • IEEE Computer Society

    Publication Year: 1987, Page(s): c2
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  • A Quantitative Comparison of the Performance of Three Discrete Distributed Associative Memory Models

    Publication Year: 1987, Page(s):257 - 263
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2548 KB)

    Monte Carlo methods have been used to study the recall accuracy of three discrete distributed associative memory models: a discrete correlation matrix model (DCM), the Bayes discriminant rule model developed by Murakami and Aibara (MA), and a discrete version of the generalized inverse model of Kohonen (DGI). The key (input) and data (output) vectors have nc components restricted to the values ... View full abstract»

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  • Processor Control Flow Monitoring Using Signatured Instruction Streams

    Publication Year: 1987, Page(s):264 - 276
    Cited by:  Papers (108)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4855 KB)

    This paper presents an innovative approach, called signatured instruction streams (SIS), to the on-line detection of control flow errors caused by transient and intermittent faults. At compile time an application program is appropriately partitioned into smaller subprograms, and cyclic codes, or signatures, characterizing the control flow of each subprogram are generated and embedded in the object... View full abstract»

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  • Derivation of Minimal Sums for Completely Specified Functions

    Publication Year: 1987, Page(s):277 - 292
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4827 KB)

    Some new concepts in switching theory are pre sented. One of these is called an "abridged minterm base." We can use an abridged minterm base instead of the minterm expansion in conventional absolute minimization procedures. Since an abridged minterm base almost always has much fewer minterms than are in the minterm expansion, we can derive an abridged minterm base for many functions for which it i... View full abstract»

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  • Vector Computer Memory Bank Contention

    Publication Year: 1987, Page(s):293 - 298
    Cited by:  Papers (41)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2087 KB)

    A number of recent vector supercomputer designs have featured main memories with very large capacities, and presumably even larger memories are planned for future generations. While the memory chips used in these computers can store much larger amounts of data than before, their operation speeds are rather slow when compared to the significantly faster CPU (central processing unit) circuitry in ne... View full abstract»

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  • Parallel Block Predictor–Corrector Methods for Ode's

    Publication Year: 1987, Page(s):299 - 311
    Cited by:  Papers (37)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3592 KB)

    The problem of achieving parallelism in the solution of the ordinary differential equations is investigated in this paper. The study focuses on an examination of block methods as a practical means for conveniently distributing the computational workload over multiple processors. Both previously suggested and newly proposed predictor-corrector formula pairs are presented and analyzed and a variable... View full abstract»

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  • Heuristic Algorithms for Single Row Routing

    Publication Year: 1987, Page(s):312 - 320
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2796 KB)

    A heuristic algorithm, based on the criterion of having nets with larger cut numbers assigned to inner tracks and nets with smaller cut numbers assigned to outer tracks, for single row routing problem has recently been proposed by Tarng et al. It has been reported that this algorithm has always been able to produce the optimal solutions for all the examples tested so far. In this paper, we have pr... View full abstract»

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  • Rectilinear Shortest Paths and Minimum Spanning Trees in the Presence of Rectilinear Obstacles

    Publication Year: 1987, Page(s):321 - 331
    Cited by:  Papers (46)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4032 KB)

    We study the rectilinear shortest paths and minimum spanning tree (MST) problems for a set of points in the plane in the presence of rectilinear obstacles. We use the track graph, a suitably defined grid-like structure, to obtain efficient solutions for both problems. The track graph consists of rectilinear tracks defined by the obstacles and the points for which shortest paths and a minimum spann... View full abstract»

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  • Pseudorandom Testing

    Publication Year: 1987, Page(s):332 - 343
    Cited by:  Papers (105)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3435 KB)

    Algorithmic test generation for high fault coverage is an expensive and time-consuming process. As an alternative, circuits can be tested by applying pseudorandom patterns generated by a linear feedback shift register (LFSR). Although no fault simulation is needed, analysis of pseudorandom testing requires the circuit detectability profile. View full abstract»

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  • Modeling the Effect of Redundancy on Yield and Performance of VLSI Systems

    Publication Year: 1987, Page(s):344 - 355
    Cited by:  Papers (59)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3518 KB)

    The incorporation of different forms of redundancy has been recently proposed for various VLSI and WSI designs. These include regular architectures, built by interconnecting a large number of a few types of system elements on a single chip or wafer. The motivation for introducing fault-tolerance (redundancy) into these architectures is two-fold: yield enhancement and performance (like computationa... View full abstract»

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  • Generating Essential Primes for a Boolean Function with Multiple-Valued Inputs

    Publication Year: 1987, Page(s):356 - 359
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (895 KB)

    Detecting essential primes is important in multiple-valued logic minimization. In this correspondence, we present a fast algorithm that can generate all essential primes without generating a prime cover of the Boolean function. A new consensus operation called asymmetric consensus (acons) is defined. In terms of acons, we prove a necessary and sufficient condition for detecting essential primes fo... View full abstract»

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  • A Probabilistic Pipeline Algorithm for K Selection on the Tree Machine

    Publication Year: 1987, Page(s):359 - 362
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (962 KB)

    We consider the problem of selecting the kth largest of n inputs, where initially the inputs are stored in the n leaf processors of the 2n − 1 processor tree machine. A probabilistic algorithm is presented that implements a type of pipelining to solve the problem in a simple data driven fashion, with each processor maintaining just a constant amount of state information. On any problem insta... View full abstract»

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  • Vectorization of the Calculation of a Moving Sum

    Publication Year: 1987, Page(s):362 - 365
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (790 KB)

    A moving sum calculation creates a vector B, such that bk is the sum of the elements ak-d through ak+d of an input vector A. It is shown that this procedure can be completely vectorized, resulting in substantial increases in execution speed. Timing comparisons for scalar and vector algorithms executed on both a 2-and a 4-pipe CYBER 205 are presented. Using 32-bit data on the 4-pipe version, the ve... View full abstract»

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  • Evaluation of On-Chip Static Interconnection Networks

    Publication Year: 1987, Page(s):365 - 369
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1140 KB)

    This correspondence evaluates three types of static interconnection networks for VLSI implementation. The criteria of evaluation have been selected from three orthogonal aspects-physical (chip area and dissipation), computational speed (message delay and message density) and cost (chip yield, operational reliability and layout cost). The main feature of this paper is to augment the selection crite... View full abstract»

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  • A New Built-In Self-Test Design for PLA's with Hligh Fault Coverage and Low Overhead

    Publication Year: 1987, Page(s):369 - 373
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1175 KB)

    This correspondence presents a new built-in self-test design for PLA's, that has a lower area overhead and higher multiple fault coverage (of three types of faults: crosspoint, stuck, and bridging) than any existing design. This new design uses function independent test input patterns (which are generated on chip), compresses the output responses into a function independent string of parity bits (... View full abstract»

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  • The Comparison Approach to Multiprocessor Fault Diagnosis

    Publication Year: 1987, Page(s):373 - 378
    Cited by:  Papers (64)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1270 KB)

    In this correspondence a system-level, comparison-based strategy for identifying faulty processors in a multiprocessor system is described. Unlike other strategies which have been proposed in the literature, the comparison approach is more efficient and relies on more realistic assumptions about the system under consideration. The new strategy is shown to correctly identify the set of faulty proce... View full abstract»

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  • A New Measure for Hybrid Fault Diagnosability

    Publication Year: 1987, Page(s):378 - 383
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1318 KB)

    Using the PMC model of a multiprocessor system, a new, general quality of hybrid fitult (combinations of hard anid soft failing units) diagnosability is characterized which encompasses previously known results as well as provides a major extension. This new diagnosability, called t/ts/τ-diagnosability, serves as a measure of the extent to which collections of test results, called syndromes, c... View full abstract»

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  • Comments on "Reliable Loop Topologies for Large Local Computer Networks"

    Publication Year: 1987, Page(s):383 - 384
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (285 KB)

    We comment on the paper by Raghavendra, Gerla, and Avizienis recently published in this TRANSACTIONS [3]. We point out a different routing strategy leading to a skip distance with diameter roughly √3N as compared to the diameter 2√N from the "optimal" skip distance obtained in that paper. View full abstract»

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  • IEEE Computer Society Publications

    Publication Year: 1987, Page(s): 384
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    Freely Available from IEEE
  • Information for authors

    Publication Year: 1987, Page(s): 384
    Request permission for commercial reuse | PDF file iconPDF (207 KB)
    Freely Available from IEEE

Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org