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IEEE Transactions on Computers

Issue 2 • Feb. 1987

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Displaying Results 1 - 23 of 23
  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1987, Page(s): c1
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  • IEEE Computer Society

    Publication Year: 1987, Page(s): c2
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  • Performance Analysis of Distributed Routing Strategies Free of Ping-Pong-Type Looping

    Publication Year: 1987, Page(s):129 - 137
    Cited by:  Papers (33)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2640 KB)

    This paper deals with a distributed adaptive routing strategy which is very simple and effective, and is free of a ping-pong-type looping in the presence of network failures. Using the number of time intervals required for a node to recover from a network failure as the measure of network's adaptability, performance of this strategy and the ARPANET's previous routing strategy (APRS) is comparative... View full abstract»

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  • Performance Models of Asynchronous Multitrunk HYPERchannel Networks

    Publication Year: 1987, Page(s):138 - 146
    Cited by:  Papers (11)  |  Patents (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2410 KB)

    The HYPERchannel communication network based on one to four trunks, or channels is considered. We develop closed queueing models with dependent servers which characterize the network performance as a function of the number of channels, the channel load, the number of stations and the packet length distribution. For analyzing the network behavior with constant packet length we introduce techniques ... View full abstract»

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  • The Fast Hartley Transform Algorithm

    Publication Year: 1987, Page(s):147 - 156
    Cited by:  Papers (111)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2307 KB)

    The fast Hartley transform (FHT) is similar to the Cooley-Tukey fast Fourier transform (FFT) but performs much faster because it requires only real arithmetic computations compared to the complex arithmetic computations required by the FFT. Through use of the FHT, discrete cosine transforms (DCT) and discrete Fourier transforms (DFT) can be obtained. The recursive nature of the FHT algorithm deriv... View full abstract»

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  • Logic Networks with a Minimum Number of NOR(NAND) Gates for Parity Functions of n Variables

    Publication Year: 1987, Page(s):157 - 166
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3277 KB)

    Design of logic networks, in single-rail input logic, with a minimum number of NOR gates for parity functions of an arbitrary number of variables is described. This is partly based on minimum networks for parity functions of a small number of variables which are designed by the integer programming logic design method. Although it is generally difficult to design minimum networks for functions of a... View full abstract»

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  • On the Schur Decomposition of a Matrix for Parallel Computation

    Publication Year: 1987, Page(s):167 - 174
    Cited by:  Papers (31)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2399 KB)

    An algorithm to solve the eigenproblem for nonsymmetric matrices on an N × N array of mesh-connected processors, isomorphic to the architecture described by Brent and Luk for symmetric matrices, is presented. This algorithm is a generalization of the classical Jacobi method, and, as such, holds promise for parallel architectures. The rotational parameters for the nonsymmetric case are careful... View full abstract»

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  • A General Model for Memory-Based Finite-State Machines

    Publication Year: 1987, Page(s):175 - 184
    Cited by:  Papers (6)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3175 KB)

    A general model of a memory-based finite-state machine architecture is introduced, the 2k− decision machine (2k− D). The classical (2n− D) and binary decision (2 − D) architectures are shown to be special cases of the 2k− D architecture. The equivalence among the 2k− D solutions for different values of k fol... View full abstract»

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  • Abstractions of Finite-State Machines Optimal with Respect to Single Undetectable Output Faults

    Publication Year: 1987, Page(s):185 - 200
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3322 KB)

    An observer, whose task is to monitor a large and complex system M̂ subject to malfunctions, may be interested in dealing with a simplified, abstracted model (M̂A of it, at the expense of some loss in fault-detection ability. Let M̂ be a finite- state machine whose inputs are modeled by stationary random variables. The abstraction A is effected by lumping M̂'s states, inputs, a... View full abstract»

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  • A New Approach to the Design of Testable PLA's

    Publication Year: 1987, Page(s):201 - 211
    Cited by:  Papers (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3261 KB)

    Programmable logic arrays (PLA's) are extensively used to realize area efficient combinational logic circuits. As the size of the PLA's increases, a cost-effective way to test them is to realize testable PLA's. In this paper a new approach to the design of testable PLA's is presented. The proposed method leads to testable PLA's with minimal area penalty and small number of tests that can be obtain... View full abstract»

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  • Using Decision Trees to Derive the Complement of a Binary Function with Multiple-Valued Inputs

    Publication Year: 1987, Page(s):212 - 214
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (598 KB)

    An algorithm to minimize decision trees of Boolean functions with multiple-valued inputs is presented. The recursive algorithm is used to obtain a complement of a sum-of-products expression for a binary function with multiple-valued inputs. In the case where each input is p-valued, the algorithm produces at most pn−l products for n-variable functions, whereas Sasao's algorithm produces pn/2 ... View full abstract»

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  • Multilevel Logical Networks

    Publication Year: 1987, Page(s):215 - 226
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1689 KB)

    In this correspondence we present a design technique for implementation of systems of Boolean functions in the form of multilevel AND-OR networks. We show that for a given system of Boolean functions, the transition from the traditional two-level AND-OR implementation to multilevel AND-OR implementations results in considerable savings in gate counts and delays. We discuss gate-array implementatio... View full abstract»

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  • Inverter-Minimum Networks

    Publication Year: 1987, Page(s):226 - 230
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (914 KB)

    Let Fm= (f1,...,fm) be a vector of m logical functions. Let Inv (Fm), the inversion complexity of Fm, be the minimum number of inverters required to realize Fm by a feed-forward network using AND gates, OR gates, and inverters. View full abstract»

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  • Algorithmic Phase Diagrams

    Publication Year: 1987, Page(s):231 - 233
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (678 KB)

    Algorithmic phase diagrams are a neat and compact representation of the results of comparing the execution time of several algorithms for the solution of the same problem. As an example we show the recent results of Gannon and Van Rosendale on the solution of multiple tridiagonal systems of equations in the form of such diagrams. The act of preparing these diagrams has revealed an unexpectedly com... View full abstract»

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  • On Linear Skewing Schemes and d-Ordered Vectors

    Publication Year: 1987, Page(s):233 - 239
    Cited by:  Papers (18)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1720 KB)

    Linear skewing schemes were introduced by Kuck et al. in the nineteen sixties, to provide a simple class of storage mappings for N × N matrices for use in vector processors with a large number of memory banks. Conditions on linear skewing schemes that guarantee conflict-free access to rows, columns, and/or (anti-) diagonals are usually presented in terms of conditions on so-called d-ordered v... View full abstract»

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  • On the Time-Bandwidth Proof in VLSI Complexity

    Publication Year: 1987, Page(s):239 - 240
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (474 KB)

    A subtle fallacy in the original proof [1] that the computation time T is lowerbounded by a factor inversely proportional to the minimum bisection width of a VLSI chip is pointed out. A corrected version of the proof using the idea of conditionally self-delimiting messages is given. View full abstract»

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  • A VLSI Implementation of the Simplex Algorithm

    Publication Year: 1987, Page(s):241 - 247
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1791 KB)

    The use of a special-purpose VLSI chip for solving a linear programming problem is presented. The chip is structured as a mesh of trees and is designed to implement the well-known simplex algorithm. A high degree of parallelism is introduced in each pivot step, which can be carried out in O (log n) time using an m × n mesh of trees having an O(mn log m log3 n) area where m − 1 and n ... View full abstract»

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  • A Computer Algorithm for Minimizing Reed-Muller Canonical Forms

    Publication Year: 1987, Page(s):247 - 250
    Cited by:  Papers (21)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (824 KB)

    A computer algorithm is presented that uses geometrical operations to minimize multioutput Reed-Muller expansions of up to ten variables. View full abstract»

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  • Rate 1/2 and 2/3 Majority Logic Decodable Binary Burst Error-Correcting Codes

    Publication Year: 1987, Page(s):250 - 252
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (541 KB)

    A new design procedure is described for constructing rate 1/2 and rate 2/3 majority logical decodable burst error-correcting codes. The rate 1/2 codes are closely related to the codes of Srinivasan [1]. View full abstract»

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  • Test Length for Pseudorandom Testing

    Publication Year: 1987, Page(s):252 - 256
    Cited by:  Papers (31)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (955 KB)

    The process of determining the required test length for a desired level of confidence for pseudorandom testing using a random sampling without replacement model is examined. The differences between random and pseudorandom testing are discussed and developed. The strictly random testing model is shown to be inaccurate for high confidence testing of combinational circuits. A method of calculating th... View full abstract»

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  • Correction to "Robust Storage Structures for Crash Recovery"

    Publication Year: 1987, Page(s): 256
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  • IEEE Computer Society Publications

    Publication Year: 1987, Page(s): 256
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    Freely Available from IEEE
  • Information for authors

    Publication Year: 1987, Page(s): 256
    Request permission for commercial reuse | PDF file iconPDF (204 KB)
    Freely Available from IEEE

Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org