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IEEE Transactions on Computers

Issue 8 • Date Aug. 1986

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Displaying Results 1 - 18 of 18
  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1986, Page(s): c1
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  • IEEE Computer Society

    Publication Year: 1986, Page(s): c2
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  • Graph-Based Algorithms for Boolean Function Manipulation

    Publication Year: 1986, Page(s):677 - 691
    Cited by:  Papers (3172)  |  Patents (138)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4062 KB)

    In this paper we present a new data structure for representing Boolean functions and an associated set of manipulation algorithms. Functions are represented by directed, acyclic graphs in a manner similar to the representations introduced by Lee [1] and Akers [2], but with further restrictions on the ordering of decision variables in the graph. Although a function requires, in the worst case, a gr... View full abstract»

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  • A Simulation Study of Decoupled Architecture Computers

    Publication Year: 1986, Page(s):692 - 702
    Cited by:  Papers (34)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4202 KB)

    Decoupled architectures achieve high scalar performance by cleanly splitting instruction processing into memory access and execution tasks. Several decoupled architectures have been proposed, and they all have two characteristics in common: 1) they have two separate sets of instructions, one for accessing memory and one for performing function execution. 2) The memory accessing task and the execut... View full abstract»

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  • Analysis of a Class of Recovery Procedures

    Publication Year: 1986, Page(s):703 - 712
    Cited by:  Papers (27)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2861 KB)

    Recovery procedures involving time redundancy in the form of instruction retries and program rollbacks have proved to be very effective against transient failures in computer systems. A class of such recovery procedures is presented and analyzed here, and the parameters of each procedure are determined so that the system's operation is optimized. These procedures are then compared in order to sele... View full abstract»

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  • Algorithms for Iterative Array Multiplication

    Publication Year: 1986, Page(s):713 - 719
    Cited by:  Papers (17)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2462 KB)

    Algorithms for the parallel multiplication of two n- bit binary numbers by an iterative array of logic cells are discussed. The regular interconnection structures of the multiplier array cell elements, which are ideal for VLSI implementation, are described. The speed and hardware complexity of two new iterative array algorithms, both of which require n-cell delays for one n-bit × n-bit multip... View full abstract»

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  • An Empirical Study of Task Switching Locality in MVS

    Publication Year: 1986, Page(s):720 - 731
    Cited by:  Papers (4)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3478 KB)

    The "hit ratio" of a high-speed buffer (cache) depends on the "locality" of memory references. However, locality of reference is disturbed and the hit ratio decreases whenever a task switch occurs. This performance degradation can be minimized if "locality of task switching," the tendency for a small set of favored tasks to be frequently executed, exists and the cache is organized in such a way th... View full abstract»

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  • Compression of Three-State Data Serial Streams by Means of a Parallel LFSR Signature Analyzer

    Publication Year: 1986, Page(s):732 - 741
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2830 KB)

    In this paper drawbacks of the three-state data compressor in the form of the unit decoder 3/2—JK flip-flop are described. The main results of the paper are the algebraic operation model and the description of detection capability of a new three-state data stream compressor consisting of decoder 3/2 and a two-input shift register TISR. In particular, the properties of the unit decoder 3/2... View full abstract»

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  • Testable Realizations for FET Stuck-Open Faults in CMOS Combinational Logic Circuits

    Publication Year: 1986, Page(s):742 - 754
    Cited by:  Papers (112)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4029 KB)

    In this paper, potential invalidation of stuck-open fault-detecting tests, derived by neglecting circuit delays and charge distribution in CMOS logic circuits, is studied. Several classes of circuits derived from sum of products and product of sums expressions for a given combinational logic function are investigated to determine the testability of FET stuck-open faults by tests which will remain ... View full abstract»

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  • An Algorithm for Optimal Logic Design Using Multiplexers

    Publication Year: 1986, Page(s):755 - 757
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (655 KB)

    A set of characterizing parameters, called ratio parameters, has been used to formulate an efficient algorithm for realizing any given Boolean funetion with a single multiplexer of minimum size. The algorithm is applicable to fuctions of a large number of variables because the conventional logic design tools, e.g., Karnaugh map, decomposition chart, etc., which are unsuitable for higher variables,... View full abstract»

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  • Reducing the Diameters of Computer Networks

    Publication Year: 1986, Page(s):757 - 761
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1116 KB)

    We discuss three methods of reducing the diameters of computer networks by adding additional processor to processor links under the constraint that no more than one I/O port be added to each processor. This is equivalent to adding edges to a given graph under the constraint that the degree of any node be increased, at most, by one. View full abstract»

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  • Prime Implicants, Minimum Covers, and the Complexity of Logic Simplification

    Publication Year: 1986, Page(s):761 - 762
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (501 KB)

    We show that any Boolean function f which can be expressed in a sum-of-products form using m product terms can contain as many as 2m− 1 implicants but no more. View full abstract»

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  • An Implementation of Mixed-Radix Conversion for Residue Number Applications

    Publication Year: 1986, Page(s):762 - 764
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (588 KB)

    A method of residue number system (RNS) conversion to mixed-radix (MR) representation is presented. This method is found to be cost-effective and efficient, particularly for moduli size 4/5 bits. A comparison of conversion times and hardware necessary for RNS conversion to MR digits based on different methods is also presented. View full abstract»

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  • Finding Lowest Common Ancestors in Parallel

    Publication Year: 1986, Page(s):764 - 769
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1305 KB)

    Two parallel algorithms for finding the lowest common ancestors of a set of vertex pairs Q (the query set) in a directed tree are presented. With all the overheads taken into account, these algorithms take O((n + QI) P log2 n) and O(n2/p + log2n) time, respectively, with p(> 0) processors (n is the size of the tree). These results are better than the best known result in that the first achieves... View full abstract»

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  • Checkpoint Faults are not Sufficient Target Faults for Test Generation

    Publication Year: 1986, Page(s):769 - 771
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (660 KB)

    Stuck-at faults on primary inputs and fan-out branches are commonly used as target faults in test generation algorithms for combinational circuits. This correspondence shows that these faults may not constitute an adequate set of target faults. A procedure is presented for selecting a set of target faults with the property that the detection of all detectable faults from this set guarantees the de... View full abstract»

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  • Calls for Papers Special Issue on Parallel and Distributed Processing

    Publication Year: 1986, Page(s): 772
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  • IEEE Computer Society Publications

    Publication Year: 1986, Page(s): 772
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  • Information for authors

    Publication Year: 1986, Page(s): 772
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org