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Computers, IEEE Transactions on

Issue 7 • Date July 1986

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Displaying Results 1 - 21 of 21
  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1986 , Page(s): c1
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  • IEEE Computer Society

    Publication Year: 1986 , Page(s): c2
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  • Editor's Notice

    Publication Year: 1986 , Page(s): 581 - 582
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  • Computer and Database Location in Distributed Computer Systems

    Publication Year: 1986 , Page(s): 583 - 590
    Cited by:  Papers (21)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2811 KB)  

    Design of distributed computer systems is a complex task requiring solutions for several difficult problems. Location of computing resources and databases in a wide-area network is one of these problems which has not yet been solved satisfactorily. Solution of this problem involves determining number and size of computer facilities and their locations, configuring databases and allocating these databases among computer facilities. An integer programming formulation of the problem is presented. Heuristic and optimal solution procedures are developed and computational experience with these procedures is reported. Implications of the model for designing distributed systems are discussed. View full abstract»

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  • Finite State Model and Compatibility Theory: New Analysis Tools for Permutation Networks

    Publication Year: 1986 , Page(s): 591 - 601
    Cited by:  Papers (25)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3254 KB)  

    In this paper, we present a new model, finite permutation machine (FPM), to describe the permutation networks. A set of theorems are developed to capture the theory of operations for the permutation networks. Using this new framework, an interesting problem is attacked: are 2n − 1 passes of shuffle exchange necessary and sufficient to realize all permutations? where n = log2 N and N is the number of inputs and outputs interconnected by the network. We prove that to realize all permutations, 2n − 1 passes of shuffle exchange are necessary and that 3n − 3 passes are sufficient. This reduces the sufficient number of passes by 2 from the best-known result. View full abstract»

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  • Pseudo-Boolean Logic Circuits

    Publication Year: 1986 , Page(s): 602 - 612
    Cited by:  Papers (24)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3084 KB)  

    A new class of switch-level logic circuits intended for modeling digital MOS VLSI circuits is presented. These circuits, which are called pseudo-Boolean, are composed of a single (voltage) source, connectors, switches, attenuators, and wells. The latter two devices are digital versions of resistors and capacitors, respectively, and may assume an arbitrary but finite number of different sizes. Signals are bidirectional, and are assigned a finite set of values of the form (v, s) where v corresponds to voltage level and s corresponds to electrical current or charge level (logical strength). It is shown that these signal values and the associated logical operations form a generalization of Boolean algebra called pseudo-Boolean or Heyting algebra. The analysis of pseudo- Boolean circuits using discrete counterparts of Kirchoff's current law and the superposition principle is discussed, as well as the application of pseudo-Boolean techniques to digital simulation. View full abstract»

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  • A Simulation Study of the CRAY X-MP Memory System

    Publication Year: 1986 , Page(s): 613 - 622
    Cited by:  Papers (30)  |  Patents (2)
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    One of the significant differences between the CRAY X-MP and its predecessor, the CRAY-1S, is a considerably increased memory bandwidth for vector operations. Up to three vector streams in each of the two processors may be active simultaneously. These streams contend for memory banks as well as data paths. All memory conflicts are resolved dynamically by the memory system. This paper describes a simulation study of the CRAY X-MP interleaved memory system with attention focused on steady state performance for sequences of vector operations. Because it is more amenable to analysis, we first study the interaction of vector streams issued from a single processor. We identify the occurrence of linked conflicts, repeating sequences of conflicts between two or more vector streams that result in reduced steady state performance. Both worst case and average case performance measures are given. The discussion then turns to dual processor interactions. Finally, based on our simulations, possible modifications to the CRAY X-MP memory system are proposed and compared. These modifications are intended to eliminate or reduce the effects of linked conflicts. View full abstract»

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  • A Triple Modular Redundancy Technique Providing Multiple-Bit Error Protection Without Using Extra Redundancy

    Publication Year: 1986 , Page(s): 623 - 631
    Cited by:  Papers (8)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2873 KB)  

    A well-known technique for providing tolerance against single hardware component failures is triplication of the component, called triple modular redundancy (TMR). In this paper a component is taken to be a processor-memory configuration where the memory is organized in a bit-sliced way. If voting is performed bitwise in an orthodox TMR configuration consisting of three of these components, failure of a complete component or failure of bit-slices not on corresponding positions in the memories can be tolerated. We present a TMR technique, not using more redundancy than orthodox TMR, that can tolerate the failure of arbitrary bit-slices (including those on corresponding positions) up to a certain amount. Additionally it can tolerate the failure of arbitrary bit-slices up to a certain amount whenever one component is known to be malfunctioning or whenever one component is disabled. This generalized TMR technique is described for processor-memory configurations processing 4-, 8-, and 16-bit words, respectively. View full abstract»

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  • Processor Scheduling for Linearly Connected Parallel Processors

    Publication Year: 1986 , Page(s): 632 - 638
    Cited by:  Papers (4)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2563 KB)  

    A low-level parallel processor (LLPP) is one in which two or more machine-level operations are executed in parallel. This paper analyzes the use of linearly connected LLPP's for parallel evaluation of program fragments. A graph-theoretic model is presented which describes the communication constraints of linearly connected parallel processors. A tight, necessary condition for finding assignments of program fragments to linearly connected LLPP's that require no communication delays is presented. Also, several weak sufficient conditions have been found and efficient heuristics for determining optimal assignments have been developed. View full abstract»

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  • On Fault Isolation and Identification in t1/t1-Diagnosable Systems

    Publication Year: 1986 , Page(s): 639 - 643
    Cited by:  Papers (24)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1083 KB)  

    Consider a classical PMC system composed of n units [1] where it is assumed that at most t1 of these units are faulty. Such a system is said to be t1/t1-diagnosable [3] if, given any complete collection of test results, the set of faulty units can be isolated to within a set of at most t1 units. This paper exposes some new, important properties of general t1/t1-diagnosable systems to present an O(n2.5) algorithm by which all the faulty units except at most one can be correctly identified and all the faulty units can be isolated to within a set of t1 or fewer units in which at most one can possibly be fault free. View full abstract»

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  • Can Redundancy and Masking Improve the Performance of Synchronizers?

    Publication Year: 1986 , Page(s): 643 - 646
    Cited by:  Papers (5)
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    This paper considers the possibility of achieving improvements in the reliability of synchronizing an asynchronous signal, by exploiting redundancy and masking. Redundancy and masking techniques have been applied successfully to mask both permanent and transient hardware faults. However, it is shown in this paper that redundancy and masking techniques are ineffective against synchronization failures which arise because of metastable behavior of synchronizing elements. View full abstract»

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  • Byte-Oriented Error-Correcting Codes for Semiconductor Memory Systems

    Publication Year: 1986 , Page(s): 646 - 648
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (655 KB)  

    Byte-oriented error-correcting codes are useful in correcting and detecting errors in a memory system organized in multiple-bit-perchip fashion. This paper presents the construction of new single-byte error-correcting and double-byte error-detecting codes. View full abstract»

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  • Complex Integer to Complex Residue Encoding

    Publication Year: 1986 , Page(s): 648 - 650
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    Recently, a new algebra for manipulating complex residue numbers was reported. Its advantage over traditional methods is a reduced complex multiplication budget. In this work a complex integer to complex residue encoder is developed for use with this new numbering system. View full abstract»

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  • Efficient Computation of the Maximum of the Sum of Two Sequences and Applications

    Publication Year: 1986 , Page(s): 651 - 653
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    Computing max{a1+ b1, a2+ b2, ... ,an+ bn} trivially takes n additions. We show that if we are given the ranking for the a's and the b's separately, then an algorithm exists which will compute the maximum in ≅2n additions on the average. This can be generalized to yield an efficient algorithm to compute max{h(a1,b1), h(a2,b2),..., h(an, bn)} where h(x,y) is monotone increasing in x and y. Another generalization shows an efficient way of computing the maximum norm of a difference between two vectors. Applications are shown in pattern classification and computational geometry. View full abstract»

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  • Pseudorandom Arrays for Built-In Tests

    Publication Year: 1986 , Page(s): 653 - 658
    Cited by:  Papers (22)  |  Patents (27)
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    Parallel pseudorandom sequences for use in built-in test are discussed. The two-dimensional nature of these sequences-makes it natural to consider the resulting binary arrays. Some of the desired properties of such arrays are discussed, as well as some of the problems. Generators for such arrays are described. A conventional LFSR with parallel output is shown to be a poor choice for such a generator. Several compact generators are described, which are shown to be compromises between complexity and varying degrees of implementation of the desired properties in the resulting sequences. One of the compact generators produces sequences which have the desired properties for built-in tests. View full abstract»

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  • Testable Design of Single-Output Sequential Machines Using Checking Experiments

    Publication Year: 1986 , Page(s): 658 - 662
    Cited by:  Papers (2)
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    The problem of testing sequential machines using checking experiments is investigated. A method of modifying sequential machines by adding a controllable input is presented. A procedure is given to construct checking experiments for the modified machine and it is shown that only one output observation is sufficient to determine whether the machine is fault free. View full abstract»

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  • Permutations on Illiac IV-Type Networks

    Publication Year: 1986 , Page(s): 662 - 669
    Cited by:  Papers (14)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1798 KB)  

    Performing permutations of data on SIMD computers efficiently is important for high-speed execution of parallel algorithms. In this correspondence we consider realizing permutations such as perfect shuffle, matrix transpose, bit-reversal, the class of bit-permute- complement (BPC), the class of Omega, and inverse Omega permutations on N = 2n processors with Illiac IV-type interconnection network, where each processor is connected to processors at distances of ± 1 and ± N. The minimum number of data transfer operations required for realizing any of these permutations on such a network is shown to be 2(N − 1). We provide a general three-phase strategy for realizing permutations and derive routing algorithms for performing perfect shuffle, Omega, Inverse Omega, bit reversal, and matrix-transpose permutations in 2(N − 1) steps. Our approach is quite simple, and unlike previous approaches, makes efficient use of the topology of the Illiac IV-type network to realize these permutations using the optimum number of data transfers. Our strategy is quite powerful: any permutation can be realized using this strategy in 3(N − 1) steps. View full abstract»

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  • An Efficient Memory System for Image Processing

    Publication Year: 1986 , Page(s): 669 - 674
    Cited by:  Papers (18)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (904 KB)  

    Image processing operations require that an image or partial image be stored in a memory system that permits access to p × q, 1 × pq, and/or pq × 1 subarrays of an image array where p and q are design parameters. View full abstract»

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  • IEEE copyright form

    Publication Year: 1986 , Page(s): 675
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  • IEEE Computer Society Publications

    Publication Year: 1986 , Page(s): 675
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    Freely Available from IEEE
  • Information for authors

    Publication Year: 1986 , Page(s): 675
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org