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IEEE Transactions on Computers

Issue 4 • Date April 1986

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Displaying Results 1 - 23 of 23
  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1986, Page(s): c1
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  • IEEE Computer Society

    Publication Year: 1986, Page(s): c2
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  • Editor's Notice

    Publication Year: 1986, Page(s): 285
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  • Fault-Tolerant Computing: An Introduction

    Publication Year: 1986, Page(s):285 - 287
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4248 KB)

    FIFTEEN years ago, the term fault-tolerant computing made its first widespread appearance in the technical literature. In March of 1971, the Digest of the First International Symposium on Fault-Tolerant Computing appeared, followed in November by the First Special Issue on Fault- Tolerant Computing of the IEEE TRANSACTIONS ON COMPUTERS. More than any other, these two publications—the Digests... View full abstract»

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  • List of referees

    Publication Year: 1986, Page(s): 287
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  • Robust Storage Structures for Crash Recovery

    Publication Year: 1986, Page(s):288 - 295
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3137 KB)

    A robust storage structure is intended to provide the ability to detect and possibly correct damage to the structure. One possible source of damage is the partial completion of an update operation, due to a "crash" of the program or system performing the update. Since adding redundancy to a structure increases the number of fields which must be changed, it is not clear whether adding redundancy wi... View full abstract»

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  • Bounds on Algorithm-Based Fault Tolerance in Multiple Processor Systems

    Publication Year: 1986, Page(s):296 - 306
    Cited by:  Papers (49)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3337 KB)

    An important consideration in the design of high- performance multiple processor systems should be in ensuring the correctness of results computed by such complex systems which are extremely prone to transient and intermittent failures. The detection and location of faults and errors concurrently with normal system operation can be achieved through the application of appropriate on-line checks on ... View full abstract»

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  • Fault-Tolerant Multiprocessors with Redundant-Path Interconnection Networks

    Publication Year: 1986, Page(s):307 - 316
    Cited by:  Papers (37)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3082 KB)

    In this paper, we study fault-tolerant multiprocessor systems employing redundant-path multistage interconnection networks. Such systems permit interprocessor communication in the presence of faulty components in the network. The interconnection network considered is a delta network augmented with an extra switching stage in front. When the first and last stages are fault-free, the extra-stage del... View full abstract»

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  • Accumulator Compression Testing

    Publication Year: 1986, Page(s):317 - 321
    Cited by:  Papers (35)  |  Patents (39)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2081 KB)

    A new test data reduction technique called accumulator compression testng (ACT) is proposed. ACT is an extension of syndrome testing. It is shown that the enumeration of errors missed by ACT for a unit under test is equivalent to the number of restricted partitions of a number. Asymptotic results are obtained for independent and dependent error modes. Comparison is made between signature analysis ... View full abstract»

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  • Calculating Cumulative Operational Time Distributions of Repairable Computer Systems

    Publication Year: 1986, Page(s):322 - 332
    Cited by:  Papers (69)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2969 KB)

    We consider repairable computer systems, those for which repair can be performed to put the system back in operation. The behavior of the system is assumed to be modeled as a homogeneous Markov process. We calculate numerically the distribution of cumulative operational time, which is the distribution of the total time during which the system was in operation over a finite observation period. The ... View full abstract»

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  • Provably Conservative Approximations to Complex Reliability Models

    Publication Year: 1986, Page(s):333 - 338
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2382 KB)

    Provably conservative (and optimistic) reliability models can be systematically derived from more complex models. These derived models incorporate a reduced state space and fewer transitions, and, therefore, have solutions that are more cost- effective than those of the original complex models. The designer can extensively explore the design space without incurring the expense of solving multiple ... View full abstract»

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  • (N, K) Concept Fault Tolerance

    Publication Year: 1986, Page(s):339 - 349
    Cited by:  Papers (21)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3499 KB)

    This paper describes a new fault-tolerant computer architecture based on a "distributed implementation" of a symbol- error correcting code. In this, as at is called, (N, K) concept the faults are masked by this code. The (N, K) concept is described in detail for N = 4 and K = 2. It is shown that symbol-error correcting codes having additional bit-error correcting capabilities make additional memor... View full abstract»

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  • Burst Unidirectional Error-Detecting Codes

    Publication Year: 1986, Page(s):350 - 353
    Cited by:  Papers (28)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (867 KB)

    Systematic codes capable of detecting burst unidrectional errors of length up to 2r−1using r check bits where r ≥ 3 are presented. Moreover, b-adjacent unidirectional error-detecting codes using [log2(b + 1)] check bits are also described. These codes are shown to be optimal or near optimal. The encoding/decoding and the totally self- checking checker design metho... View full abstract»

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  • An Efficient Algorithm for Identifying the Most Likely Fault Set in a Probabilistically Diagnosable System

    Publication Year: 1986, Page(s):354 - 356
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (658 KB)

    An O(n3) algorithm is given for determining the most likely set of faulty processors in a class of systems introduced by Maheshwari and Hakimi[6], known as probabilistically diagnosable systems. The technique uses the a priori probability of failure of each unit combined with the results of tests which the processors administer to one another to perform diagnosis. The algorithm uses wel... View full abstract»

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  • A Fault-Tolerant Modular Architecture for Binary Trees

    Publication Year: 1986, Page(s):356 - 361
    Cited by:  Papers (44)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1306 KB)

    A new modular, fault-tolerant scheme is proposed for the binary tree architecture. The approach uses redundant modular fault- tolerant building blocks to construct the complete binary tree. The restructuring operation is local to each faulty module. The proposed scheme is shown to be more reliable and easier to implement than the existing fault-tolerant schemes. View full abstract»

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  • Test Schedules for VLSI Circuits Having Built-In Test Hardware

    Publication Year: 1986, Page(s):361 - 367
    Cited by:  Papers (40)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1474 KB)

    In this correspondence, the concept of a test schema which describes how a test methodology is to execute is introduced. We also introduce the powerful concept of an I path which is used to transfer data unchanged from one place in a circuit to another. The process of embedding a test schema into an actual circuit is described. This produces a test plan for the circuit which specifies the sequence... View full abstract»

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  • Condensed Linear Feedback Shift Register (LFSR) Testing—A Pseudoexhaustive Test Technique

    Publication Year: 1986, Page(s):367 - 370
    Cited by:  Papers (37)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (870 KB)

    This paper presents a design technique for linear feedback shift registers that generate test patterns for pseudoexhaustive testing. This technique is applicable to any combinational network in which none of the outputs depends on all inputs. It does not rewire the original network inputs during in-circuit test pattern generation. Thus, the possibility of undetected faults on some inputs is elimin... View full abstract»

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  • Measurement and Application of Fault Latency

    Publication Year: 1986, Page(s):370 - 375
    Cited by:  Papers (36)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1314 KB)

    The time interval between the occurrence of a fault and the detection of the error caused by the fault is divided by the generation of that error into two parts: fault latency and error latency. Since the moment of error generation is not directly observable, all related works in the literature have dealt with only the sum of fault and error latencies, thereby making the analysis of their separate... View full abstract»

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  • Functional Test Generation for Digital Circuits Described Using Binary Decision Diagrams

    Publication Year: 1986, Page(s):375 - 379
    Cited by:  Papers (24)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1073 KB)

    This correspondence presents a test generation methodology for VLSI circuits described at the functional level. A VLSI circuit is modeled as a network of functional modules such as registers, adders, RAM's, and MUX's. The functions of the individual modules are described using binary decision diagrams. A functional fault model is developed independent of the implementation details of the circuit. ... View full abstract»

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  • Lower Overhead Design for Testability of Programmable Logic Arrays

    Publication Year: 1986, Page(s):379 - 383
    Cited by:  Papers (34)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1188 KB)

    A new technique for designing easily testable PLA's is presented. The salient features of this technique are: 1) low overhead, 2) high fault coverage, 3) simple design, and 4) little or no impact on normal operation of PLA's. This technique consists of the addition of input lines in such a way that, in test mode, any single product line can be activated and its associated circuitry and device can ... View full abstract»

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  • An Alternative to Scan Design Methods for Sequential Machines

    Publication Year: 1986, Page(s):384 - 388
    Cited by:  Papers (10)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (723 KB)

    The problem of testing sequential machines using a checking experiment is investigated. An algorithm is given to augment sequential machines by adding extra input(s) to make them testable. We also present a circuit modification method, similar to scan methods, such that the augmented machine can be tested by the checking experiment. A justification of our method for a VLSI environment is given by ... View full abstract»

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  • IEEE Computer Society Publications

    Publication Year: 1986
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  • Information for authors

    Publication Year: 1986, Page(s): 388
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org