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Computers, IEEE Transactions on

Issue 2 • Date Feb. 1986

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Displaying Results 1 - 18 of 18
  • IEEE Transactions on Computers - Table of contents

    Page(s): c1
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  • IEEE Computer Society

    Page(s): c2
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  • Introduction—Multiple-Valued Logic

    Page(s): 97 - 98
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    MULTIPLE-valued logic has been the object of much research over the last fifteen years. Since 1971, there has been an annual symposium devoted exclusively to the subject and, during that time, nearly 600 papers have appeared in its Proceedings. In addition, a large number of technical papers have appeared elsewhere together with a number of survey articles [1]-[4] and a number of textbooks [5]-[7]. Much of the older work was of a purely theoretical nature concerned with the functional completeness of sets of operators, functional minimization, and similar problems from switching theory and logic design. Work on the hardware implementation of multiple-valued devices has been more recent (see [8] for an early discussion). View full abstract»

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  • A Survey of Multivalued Memories

    Page(s): 99 - 106
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    Techniques of storing multiple bits of information in a single memory location are reviewed. Any of several states can be stored in ROM's by adjusting the threshold voltage or the size of a particular memory device. In dynamic RAM's, this can be achieved by varying the charge stored on the cell capacitor. The peripheral circuitry required to distinguish between the states stored in the memory areas is discussed. View full abstract»

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  • Uncertainty, Energy, and Multiple-Valued Logics

    Page(s): 107 - 114
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    The multiple-valued logics obtained by introducing uncertainty and energy considerations into classical switching theory are studied in this paper. First, the nature of uncertain or unknown signals is examined, and two general uncertainty types called U-values and P-values are identified. It is shown that multiple-valued logics composed of U/P-values can be systematically derived from 2-valued Boolean algebra. These are useful for timing and hazard analysis, and provide a rigorous framework for designing gate-level logic simulation programs. Next, signals of the form (v, s) are considered where v and s denote logic level and strength, respectively, and the product vs corresponds to energy flow or power. It is shown that these signals form a type of lattice called a pseudo-Boolean algebra. Such algebras characterize the behavior of digital circuits at a level (the switch level) intermediate between the conventional analog and logical levels. They provide the mathematical basis for an efficient new class of switch-level simulation programs used in MOS VLSI design. View full abstract»

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  • Complexity Based on Partitioning of Boolean Circuits and their Relation to Multivalued Circuits

    Page(s): 115 - 123
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    We present a new complexity measure for Boolean functions based on partitions of combinatorial circuits into subcircuits, and give upper and lower bounds on the complexity for Boolean functions. Roughly speaking, for a function g whose range is the set of positive integers, g(n)-partition of a circuit is a partition of a circuit into subcircuits such that. 1) each subcircuit has at most g(n) output gates, through which gates in the subcircuit are connected to gates in another succeeding subcircuits and 2) each subcircuit has at most two preceding subcircuits where subcircuit N1 (N2) is said to precede (succeed) subcircuit N2 (N1) when there is a line directed from a gate in N1 to a gate in N2. Our main result, which is stated in terms of a lower bound theorem and an upper bound theorem, is a precise version of the following statement: For "almost all" n-argument Boolean functions fn, the minimum nu mber of subcircuits over g n)-partition of a circuit to compute fn is given as (2n/g(n)22g(n)) unless g(n) grows much more slowly than n as n increases. To prove the theorems, we regard a Boolean circuit, together with g(n)-partition of it, as the multivalued circuit composed of multivalued gates corresponding to the subcircuits obtained from the g(n)-partition. View full abstract»

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  • Synthesis of Multivalued Multithreshold Functions for CCD Implementation

    Page(s): 124 - 133
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    Basic multivalued building blocks constructed using CCD (charge-coupled devices) technology are presented. They are used to realize simple threshold functions. Existing techniques for decomposition of multivalued multithreshold functions into simpler subfunctions are reviewed. Usage of the CCD technology in implementation of these subfunctions is discussed. Two new decomposition techniques are proposed. Their aim is to obtain realizations that are better suited to CCD technology in terms of the maximum number of thresholds per element and the generation of negative weights. Synthesis techniques based on the proposed decompositions are presented and compared. Although 4-valued logic functions are stressed, the techniques are, in principle, applicable to functions of any radix. View full abstract»

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  • Heuristic Minimization of MVL Functions: A Direct Cover Approach

    Page(s): 134 - 144
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    A heuristic method to obtain near-minimal covers of p-valued switching functions is introduced. First, we describe transform tools useful in the processing of MVL functions. They are: p-adic shifting, weighting, and implicant detecting transformations. Based on these tools, a direct cover algorithm is presented that uses local information for heuristic decision making. The heuristics are taken from weight coefficients calculated for canonical terms and implicants. The method allows to assign cost factors to implicants. Further, the algorithms can be modified easily, so as to correspond to various connectives (e.g., MAX, PLUS). View full abstract»

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  • Representation of Uncertainty in Computer Vision Using Fuzzy Sets

    Page(s): 145 - 156
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    Uncertainty in computer vision can arise at various levels. It can occur in the low level in the raw sensor input, and extends all the way through intermediate and higher levels. Ideally, at any level where decisions are being made on the basis of previous processing steps, a computer vision system must have sufficient flexibility for representation of uncertainty in any of these levels. View full abstract»

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  • Characteristics of Prototype CMOS Quaternary Logic Encoder-Decoder Circuits

    Page(s): 157 - 161
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    The use of quaternary logic input and output signals for delivering information on and off chip could reduce the number of required package pins or increase the amount of information conveyed on a fixed number of package pins. In this correspondence, we discuss the performance of prototype CMOS binary-to-quaternary encoder and quaternary-to-binary decoder test circuits that have been realized on a gate array IC chip. View full abstract»

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  • The Current Mode Fuzzy Logic Integrated Circuits Fabricated by the Standard CMOS Process

    Page(s): 161 - 167
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    Nine basic fuzzy logic circuits employing p-ch and n-ch current mirrors are presented, and the fuzzy information processing hardware system design at a low cost with only one kind of master slice (semicustom fuzzy logic IC) is described. The fuzzy logic circuits presented here will be indispensable for a "fuzzy computer" in the near future. View full abstract»

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  • Ternary Scan Design for VLSI Testability

    Page(s): 167 - 170
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    In this correspondence, a new scheme is proposed in which ternary clocking signals are used to replace binary clocking signals in VLSI scan-testing designs. This scheme has the same advantage of high testability as the binary scan method [1], but it eliminates the mode- selecting signal line. Since this mode-selecting line must be routed to each flip-flop in the binary scan scheme, the saving is significant in reducing the circuit interconnection complexity and chip area. This correspondence describes the new ternary scheme in detail, and also suggests appropriate circuit designs using CMOS technology. Furthermore, comparisons are made between ternary scan and binary scan [3] and between ternary scan and a scan scheme using binary with a local decoder [2]. View full abstract»

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  • On the Diagnosability of a General Model of System with Three-Valued Test Outcomes

    Page(s): 170 - 173
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    The problem of diagnosability of a system with three-valued test outcomes was considered in earlier works [1]-[3]. However all these works assume the system to be modeled as in [4]. In this correspondence, we consider a more general model of the system and study the diagnosability criteria in presence of three-valued test outcomes. In this model, each unit is tested jointly by a number of other units of the system as opposed to each test being carried out by a single unit of the system as in [4]. Necessary and sufficient conditions for the diagnosability of a system under this general model have been presented in this correspondence. Throughout the correspondence, diagnosability without repair has been considered. View full abstract»

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  • Iteration Properties of Multivalued Switching Functions

    Page(s): 173 - 178
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    The purpose of this correspondence is to survey the literature concerning the iterative properties of multivalued switching functions. These properties are important for the synthesis of switching circuits by cascades of simpler elements. Our presentation evolves around the graphs of transformations of finite sets. We discuss such topics as limitations of the computational capabilities of cascades, the existence of roots of given functions with respect to iteration powers, etc. View full abstract»

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  • Regular Ternary Logic Functions—Ternary Logic Functions Suitable for Treating Ambiguity

    Page(s): 179 - 183
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    A special group of ternary functions, called regular ternary logic functions, are defined. These functions are useful in switching theory, programming languages, algorithm theory, and many other fields—if we are concerned with the indefinite state in such fields. This correspondence describes the fundamental properties and representations of the regular ternary logic functions. View full abstract»

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  • Design of a Multiple-Valued Systolic System for the Computation of the Chrestenson Spectrum

    Page(s): 183 - 188
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    This correspondence deals with the computation of the Chrestenson spectrum of an n-ary, n-place, p-valued function by means of a systolic system. The design of a systolic system in a multiple-valued environment is discussed in details and some aspects are compared to binary realizations. View full abstract»

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  • IEEE Computer Society Publications

    Page(s): 188
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    Freely Available from IEEE
  • Information for authors

    Page(s): 188
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Albert Y. Zomaya
School of Information Technologies
Building J12
The University of Sydney
Sydney, NSW 2006, Australia
http://www.cs.usyd.edu.au/~zomaya
albert.zomaya@sydney.edu.au