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IEEE Transactions on Computers

Issue 11 • Date Nov. 1986

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Displaying Results 1 - 14 of 14
  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1986, Page(s): c1
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  • IEEE Computer Society

    Publication Year: 1986, Page(s): c2
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  • Roving Emulation as a Fault Detection Mechanism

    Publication Year: 1986, Page(s):933 - 939
    Cited by:  Papers (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2646 KB)

    In this paper we present a new built-in test methodology for detecting and locating faults in digital systems. The technique is called roving emulation and consists of an off-line snap shot type emulation or simulation of operating components in a system. Its primary application is in testing systems in the field where real-time fault detection is not required. The primary performance measure of t... View full abstract»

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  • A Formal Definition of Data Flow Graph Models

    Publication Year: 1986, Page(s):940 - 948
    Cited by:  Papers (32)  |  Patents (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3651 KB)

    In this paper, a new model for parallel computations and parallel computer systems that is based on data flow principles is presented. Uninterpreted data flow graphs can be used to model computer systems including data driven and parallel processors. A data flow graph is defined to be a bipartite graph with actors and links as the two vertex classes. Actors can be considered similar to transitions... View full abstract»

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  • A LOTOS Specification of the PROWAY Highway Service

    Publication Year: 1986, Page(s):949 - 968
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4372 KB)

    The Language for temporal ordering specification (LOTOS) is a formal description technique whose development is under way within ISO, the International Organization for standardization, mainly for application to open systems interconnection (OSI) standards. The paper presents a LOTOS specification of the PROWAY interface for process control applicatioins, defined by IEC, the International Electrot... View full abstract»

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  • Multigrid Algorithms on the Hypercube Multiprocessor

    Publication Year: 1986, Page(s):969 - 977
    Cited by:  Papers (49)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3008 KB)

    This paper examines several ways of implementing multigrid algorithms on the hypercube multiprocessor. We consider both the standard multigrid algorithms and a concurrent version proposed by Gannon and Van Rosendale. We present several mappings of the mesh points onto the nodes of the cube. The main property of these mappings, which are based on binary reflected Gray codes, is that the distance be... View full abstract»

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  • Synchronized Disk Interleaving

    Publication Year: 1986, Page(s):978 - 988
    Cited by:  Papers (78)  |  Patents (96)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3418 KB)

    A group of disks may be interleaved to speed up data transfers in a manner analogous to the speedup achieved by main memory interleaving. Conventional disks may be used for interleaving by spreading data across disks and by treating multiple disks as if they were a single one. Furthermore, the rotation of the interleaved disks may be synchronized to simplify control and also to optimize performanc... View full abstract»

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  • Synthesis of an Optimal Family of Matrix Multiplication Algorithms on Linear Arrays

    Publication Year: 1986, Page(s):989 - 996
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1786 KB)

    Synthesis of a family of matrix multiplication algorithms on a linear array is described. All these algorithms are optimal in their area and time requirements. An important feature of the family of algorithms is that they are modularly extensible, that is, larger problem sizes can be handled by cascading smaller arrays consisting of processors having a fixed amount of local storage. These algorith... View full abstract»

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  • Row/Column Replacement for the Control of Hard Defects in Semiconductor RAM's

    Publication Year: 1986, Page(s):996 - 1000
    Cited by:  Papers (7)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (881 KB)

    We describe and analyze row/column replacement, the technique currently used to control hard cell defects in semiconductor RAM's during manufacture. This strategy is shown to be asymptotically ineffective; it is demonstrated that this ineffectiveness may become a limiting issue for very large memory arrays. View full abstract»

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  • A Parallel Algorithm to Compute the Shortest Paths and Diameter of a Graph and Its VLSI Implementation

    Publication Year: 1986, Page(s):1000 - 1004
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1036 KB)

    In this correspondence we develop a parallel algorithm to compute the all-pairs shortest paths and the diameter of a given graph. Next, this algorithm is mapped into a suitable VLSI systolic architecture and the performance of this proposed VLSI implementation is evaluated. View full abstract»

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  • An Algorithm for Determining the Fault Diagnosability of a System

    Publication Year: 1986, Page(s):1004 - 1008
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1137 KB)

    The fault diagnosability problem is the problem of computing the maximum number of faulty units which a system can tolerate without losing its capability of identifying all such faulty units. We study this problem for the model introduced by Barsi, Grandoni, and Maestrini [2]. We present a new characterization of the model, and develop an efficient diagnosability algorithm for a system in this mod... View full abstract»

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  • Techniques for Computing the Discrete Fourier Transform Using the Quadratic Residue Fermat Number Systems

    Publication Year: 1986, Page(s):1008 - 1012
    Cited by:  Papers (4)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (701 KB)

    In this correspondence, the complex integer multiplier and adder over the direct sum of two copies of finite field developed in [1] is specialized to the direct sum of the rings of integers modulo Fermat numbers. Such multiplication over the rings of integers modulo Fermat numbers can be performed by means of two integer multiplications, whereas the complex integer multiplication requires three in... View full abstract»

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  • IEEE Computer Society Publications

    Publication Year: 1986, Page(s): 1012
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    Freely Available from IEEE
  • Information for authors

    Publication Year: 1986, Page(s): 1012
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org