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IEEE Transactions on Computers

Issue 10 • Date Oct. 1986

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Displaying Results 1 - 19 of 19
  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1986, Page(s): c1
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  • IEEE Computer Society

    Publication Year: 1986, Page(s): c2
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  • Algorithmic State Machine Design and Automatic Theorem Proving: Two Dual Approaches to the Same Activity

    Publication Year: 1986, Page(s):853 - 861
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2476 KB)

    This paper shows that synthesizing binary decision programs (formed by means of decision instructions of the type if then else and of execution instructions of the type do) and proving theorems can be carried out by using the same approach. It is proved that the same transformations acting on P-functions can be interpreted in terms of binary program synthesis and of theorem proving. Since binary p... View full abstract»

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  • Built-In Testing of Memory Using an On-Chip Compact Testing Scheme

    Publication Year: 1986, Page(s):862 - 870
    Cited by:  Papers (33)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2945 KB)

    In this paper we study the problem of testing RAM. A new fault model, which encompasses the existing fault models, is proposed. We then propose a scheme of testing faults from the new fault model using built-in testing techniques. We introduce concept of p-hard and determine the complexity of the extra hardware required for built-in self-testing on our hardness scale. A novel approach using microc... View full abstract»

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  • Distributed Recovery in Fault-Tolerant Multiprocessor Networks

    Publication Year: 1986, Page(s):871 - 879
    Cited by:  Papers (21)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3116 KB)

    A methodology for characterizing dynamic distributed recovery in fault-tolerant multiprocessor systems is developed using graph theory. Distributed recovery, which is intended for systems with no central supervisor, depends on the cooperation of a set of processors to execute the recovery function, since each processor is assumed to have only a limited amount of information about the system as a w... View full abstract»

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  • Clocking Schemes for High-Speed Digital Systems

    Publication Year: 1986, Page(s):880 - 895
    Cited by:  Papers (77)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4303 KB)

    A key element (one is tempted to say the heart) of most digital systems is the clock. Its period determines the rate at which data are processed, and so should be made as small as possible, consistent with reliable operation. View full abstract»

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  • A Signed Bit-Sequential Multiplier

    Publication Year: 1986, Page(s):896 - 901
    Cited by:  Papers (11)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2090 KB)

    Bit-sequential algorithms for arithmetic processing are good candidates for VLSI signal processing circuits because of their canonical structure and minimal interconnection requirements. Several recent papers have dealt with algorithms that accept unsigned binary inputs, one bit at a time, least significant bit first, and produce an unsigned binary product in a bit-serial fashion. View full abstract»

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  • Analysis of Performability for Stochastic Models of Fault-Tolerant Systems

    Publication Year: 1986, Page(s):902 - 907
    Cited by:  Papers (58)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1370 KB)

    Performability, a composite measure for the performance and reliability, may be interpreted as the probability density function of the aggregate reward obtained from a system during its mission time. For large mission times we show that known limit theorems lead to an asymptotic normal distribution for the aggregate reward. For finite mission times and Markovian models we obtain the expressions fo... View full abstract»

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  • Comments on "A Massive Memory Machine"

    Publication Year: 1986, Page(s):907 - 910
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1109 KB)

    Garcia-Molina, Lipton, and Valdes [1] introduced a new machine architecture called "massive memory machines" (MMM). The primary application of their proposed architecture was for so-called memory bound computations. In this correspondence we argue: 1) that massive memories will likely become feasible, but will be most effective with much more powerful processors, and 2) that a massive memory on th... View full abstract»

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  • Reconfiguration Procedures for a Polymorphic and Partitionable Multiprocessor

    Publication Year: 1986, Page(s):910 - 916
    Cited by:  Papers (15)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1579 KB)

    This correspondence presents a collection of reconfiguration procedures for a multiprocessor which employs multistage interconnection networks. These procedures are used to dynamically partitipn the multiprocessor into many subsystems, and reconfigure them to form a variety commonly used topologies to match task graphs. By examining the switching capability of the interconnection network, design r... View full abstract»

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  • Dual Systolic Architectures for VLSI Digital Signal Processing Systems

    Publication Year: 1986, Page(s):916 - 923
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1475 KB)

    This correspondence presents a linear systolic array for the implementation pf digital signal processing systems based upon matrix- vector multiplication algorithms where the matrix elements can be computed from their row and column indexes. Haar, Walsh, and the discrete Fourier transforms are solved using this approach. The method presented enables the n2 matrix elements to be computed in situ di... View full abstract»

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  • A VLSI Solution to the Vertical Segment Visibility Problem

    Publication Year: 1986, Page(s):923 - 928
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1183 KB)

    We present a parallel algorithm to solve the visibility problem among n vertical segments in a plane, which can be implemented on a VLSI chip arranged as a mesh of trees. Our algorithm determines all the pairs of segments that "see" each other in time O(log n); while the fastest sequential algorithm requires O(n log n). A lower bound to the area-time complexity of this problem of O(n2 log2 n) is a... View full abstract»

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  • Comments on "Matrix Processors Using p-Adic Arithmetic for Exact Linear Computations"

    Publication Year: 1986, Page(s):928 - 930
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (460 KB)

    The addition and multiplication algorithms of two Hensel codes were presented in two earlier papers [1], [2] on p-adic arithmetic. It is shown here that these algorithms do not always generate a correct result having the same code word length as the two operands and the correct algorithms are given. View full abstract»

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  • Comments on "Detection of Faults in Programmable Logic Arrays"

    Publication Year: 1986, Page(s):930 - 931
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (299 KB)

    This correspondence shows two counter examples which contradict the Theorems 4 and 5 in [1]. View full abstract»

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  • Author's Reply

    Publication Year: 1986, Page(s): 931
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (177 KB)

    The paper by Schertz and Metze [1] is concerned with combinational circuits having a certain restricted fan-out structure. Two-level circuits have this restricted structure. A PLA as defined in [2] with only G and D faults behaves like a two-level combinational circuit with stuck-at faults. Hence, the results of Schertz and Metze are applicable. In an AND-OR PLA, a G fault is equivalent to a stuck... View full abstract»

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  • Author's reply1

    Publication Year: 1986, Page(s): 932
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  • Correction to "Lower Bounds for Sorting with Realistic Instruction Sets"

    Publication Year: 1986, Page(s): 932
    Cited by:  Papers (3)
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  • IEEE Computer Society Publications

    Publication Year: 1986, Page(s): 932
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    Freely Available from IEEE
  • Information for authors

    Publication Year: 1986, Page(s): 932
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org