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Computers, IEEE Transactions on

Issue 1 • Date Jan. 1986

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Displaying Results 1 - 24 of 24
  • IEEE Transactions on Computers - Table of contents

    Page(s): c1
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  • IEEE Computer Society

    Page(s): c2
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  • Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays

    Page(s): 1 - 12
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    A technique for partitioning and mapping algorithms into VLSI systolic arrays is presented in this paper. Algorithm partitioning is essential when the size of a computational problem is larger than the size of the VLSI array intended for that problem. Computational models are introduced for systolic arrays and iterative algorithms. First, we discuss the mapping of algorithms into arbitrarily large size VLSI arrays. This mapping is based on the idea of algorithm transformations. Then, we present an approach to algorithm partitioning which is also based on algorithm transformations. Our approach to the partitioning problem is to divide the algorithm index set into bands and to map these bands into the processor space. The partitioning and mapping technique developed throughout the paper is summarized as a six step procedure. A computer program implementing this procedure was developed and some results obtained with this program are presented. View full abstract»

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  • Testability Conditions for Bilateral Arrays of Combinational Cells

    Page(s): 13 - 22
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    Two sets of conditions are derived that make one- dimensional bilateral arrays of combinational cells testable for single faulty cells. The test sequences are preset and, in the worst case, grow quadratically with the size of the array. Conditions for testability in linear time are also derived. The basic cell can operate at the bit or at the word level. An implementation of FIR filters using (systolic) one-dimensional bilateral arrays of cells, which can be considered combinational at the word level, is presented as an example. A straightforward generalization for the two- dimensional case is made; a systolic array used for matrix multiplication is presented as an example for this case. View full abstract»

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  • DFSP: A Data Flow Signal Processor

    Page(s): 23 - 33
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    The concept of data flow computing is applied to digital signal processing (DSP). A data flow signal processor (DFSP) architecture is presented. The principles of data flow computing are carefully considered in order to conform with the special properties of DSP. The bus oriented architecture is easily configured to meet various performance requirements. The DFSP architecture is most suitable for nonrecursive algorithms. Typical tasks of this nature are transforms and FIR filters. A simulation model of the DFSP architecture has been developed. Simulation results of two application examples are given. View full abstract»

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  • A Heuristic for Suffix Solutions

    Page(s): 34 - 42
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    The suffix problem has appeared in solutions of recurrence systems for parallel and pipelined machines and more recently in the design of gate and silicon compilers. In this paper we present two algorithms. The first algorithm generates parallel suffix solutions with minimum cost for a given length, time delay, availability of initial values, and fanout. This algorithm generates a minimal solution for any length n and depth range from log2 n to n. The second algorithm reduces the size of the solutions generated by the first algorithm. View full abstract»

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  • Determining an Optimal Secondary Storage Service Rate for the PASM Control System

    Page(s): 43 - 53
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    One class of reconfigurable parallel processing systems is based on the use of a large number of processing elements which can be partitioned into multiple virtual machines. Each virtual machine is controlled by one or more control units. The multiple control units in such a system share a common secondary storage for programs. The control units use paging to transfer programs to their primary memories. One design problem is determining the optimal service rate for the secondary storage of the control units, where the "optimal" is characterized by maximum processor utilization. The PASM parallel processing system is used as a example system to study this problem. The implementation of virtual memory on the PASM control system memory hierarchy is discussed and a queueing network model for the memory hierarchy is developed. Based on assumed values for parameters that characterize the expected task environment, an optimal service rate is derived from the model. The values of the parameters in the model can be varied to determine the impact these changes would have on system performance. Simulation results verifying various aspects of the model are presented and the results are generalized. View full abstract»

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  • An Enhanced Approximation by Pair-Wise Analysis of Servers for Time Delay Distributions in Queueing Networks

    Page(s): 54 - 61
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    An approximation for the distribution of time delays experienced by a customer in a network of queues is presented. Approximate analytical models are necessary since exact solutions are only available for a very restricted class of networks, and are too complex computationally to be viable in practice. Approximations have so far often proved inadequate, particularly for closed networks with first come first served queueing disciplines. We also prove that the correlation between the sojourn times at successive servers on a customer's path in a closed queueing network with exponential servers is negative. View full abstract»

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  • Optimal Bounds for Finding Maximum on Array of Processors with k Global Buses

    Page(s): 62 - 64
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    The problem of finding the maximum of a set of values stored one per processor on a two-dimensional array of processors with a time-shared global bus is considered. The algorithm given by Bokhari is shown to be optimal, within a multiplicative constant, for this network and for other d-dimensional arrays. We generalize this model and demonstrate optimal bounds for finding the maximum of a set of values stored in a d-dimensional array with k time-shared global buses. View full abstract»

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  • The Bidirectional Double Latch (BDDL)

    Page(s): 65 - 66
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    This paper describes a new type of shift register latch that is compatible with LSSD. The new latch has the property that information may be shifted in and out of it in two directions: left to right and right to left. View full abstract»

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  • Asynchronous Modular Arbiter

    Page(s): 67 - 70
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    A practical N-user arbiter and its implementation are presented in this correspondence. Because of the asynchronous character of its input variables (request signals), the design proposed is asynchronous and keeps in mind the possibility of metastable operations. The structure of the arbiter is very simple and modular. View full abstract»

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  • Deductive Fault Simulation of Internal Faults of Inverter-Free Circuits and Programmable Logic Arrays

    Page(s): 70 - 73
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    A method for the deductive fault simulation of faults in inverter-free circuits is presented. It is shown that in an inverter-free circuit, fault lists on lines with complementary logic values are disjoint, and fault list calculations can be done by performing fewer set operations compared to conventional gate level deductive simulation. Applications of the method to programmable logic arrays (PLA's) and deductive fault simulation of PLA faults are discussed. View full abstract»

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  • A Note on the Restricted Range Cutting Algorithm

    Page(s): 73
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    In [1], an algorithm to compute bounds on signal probabilities in VLSI nets is provided. View full abstract»

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  • Systolic Algorithnis for Local Operations on Images

    Page(s): 73 - 77
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    Local operators, used in many image processing tasks, involve replacing each pixel in an image with a value computed within a local neighborhood of that pixel. Computing such operators at the video rate requires a computing power which is not provided by conventional computers. Though computationally expensive, local operators are highly regular. Thus, a VLSI implementation appears particularly appropriate. This correspondence presents systolic algorithms for tasks such as connected component determination, distance transform, and relaxation, which are defined in terms of local operators. View full abstract»

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  • Global Flow Analysis in Automatic Logic Design

    Page(s): 77 - 81
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    This correspondence concerns applications of optimization techniques based on global flow analysis to the automated design of logic. Previous optimization work on logic design has relied primarily on either local transformations on the circuit graph or on the use of two-level Boolean minimization. Our methods involve linear time algorithms which extend the scope of local optimizations to the entire design. Their use, in some cases, has resulted in a reduction in gate count, in improved control over path length, and in better detection and elimination of redundancy. View full abstract»

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  • The Influence of Masking Phenomenon on Coverage Capability of Single Fault Test Sets in PLA's

    Page(s): 81 - 85
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    It is relatively easy to generate a complete single contact fault detection test set Tc for a PLA. However such a test set may fail to detect all multiple faults due to the phenomenon of masking. In previous papers attempting to quantitatively predict the multiple fault coverage capability of a single fault detection test set Tc in PLA's, it was proved that every multiple contact fault in an irredundant PLA is detected by Tc if the multiple fault does not contain any four-way masking cycle. In this correspondence, the masking relations are studied in detail and it is shown that Tc in fact detects a signifilcant percentage of faults with four-way masking. Based on these results more realistic bounds of the coverage capability of Tc are determined. It is shown that the multiple fault coverage ratio of Tc increases with the increasing number m of rows of a PLA and for m = 24 Tc detects 99 percent of all contact faults of size 8 or less. View full abstract»

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  • On the Impossible Class of Faulty Functions in Logic Networks Under Short Circuit Faults

    Page(s): 85 - 90
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    The important problem of recognizing a priori the class of Boolean functions which are never obtainable from a given combinational network under short circuit faults is almost unexplored, primarily due to lack of understanding of the functional and structural factors that influence the fault behavior in the network. In view of this, a new concept of impossible class of faulty functions (ICFF) is introduced in this correspondence. Several intriguing properties of ICFF are uncovered, namely, the undetectability of input bridging faults, the impossibility of the transformation of a fault free function Fo to a subset or superset of Fo, and to other functions belonging to the same P-and N-equivalence classes of Fo, etc. The closure amongst the fan-out-free and unate functions under bridging faults is investigated. The impact of ICFF on the testability of the network is also discussed. View full abstract»

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  • On System Diagnosability in the Presence of Hybrid Faults

    Page(s): 90 - 93
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    This correspondence deals with the problem of testing the diagnosmbllity of a system in presence of hybrid faults (that is, when some of the units of the system have failed intermittently and some have failed permanently). Presence of intermittent faults can lead to incomplete diagnosis and usually complicates the diagnosis problem in comparison to permanent fault situation. Alternative characterizations for hybrid fault diagnosability of a system to those originally presented in [3] are derived in this paper. It is shown that these conditions lead to the testing of the hybrid diagnosability of a system with fewer computations than that in [3]. View full abstract»

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  • Comments on "The Diogenes Approach to Testable Fault-Tolerant Arrays of Processors"

    Page(s): 93
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    The above paper1presents an approach to the design of fault- tolerant processor arrays. In Section IV of this paper (related work on fault-tolerant networks) the author criticizes a previously published approach presented by Koren [1] and by Gordon, Koren and Silberman [2]. In [1], an algorithm for structuring a linear array on a rectangular grid of processing elements (PE's), some of which may be faulty, is presented. Since similar structuring algorithms for other structures like square arrays and binary trees (in the presence of faulty PE's) are more complicated, a different strategy has been suggested in [1]. According to it, all PE's in the same row or column of the faulty processor will turn into connecting elements (CE's) and will not participate in any future processing task. The remaining PE's still constitute a rectangular grid with one less row and one less column. Consequently, the same structuring algorithms (for fault- free arrays) can be used and in many cases the grid will admit the same size of a binary tree as before [1]. If the communication link between two neighboring processors fails, only the processors within the corresponding single row or column will be declared CE's. In [2], a similar strategy has been applied to hexagonal arrays. View full abstract»

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  • Author's Reply2

    Page(s): 93 - 94
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    Professor Koren's comments on my paper raise a number of points that merit more attention than they typically receive in the literature. View full abstract»

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  • Correction to "Fault-Tolerant Multiprocessor Link and Bus Architectures"

    Page(s): 94
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    In the above paper1 the following typographical errors should be corrected. View full abstract»

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  • IEEE copyright form

    Page(s): 95
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  • IEEE Computer Society Publications

    Page(s): 95
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  • Information for authors

    Page(s): 95
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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org