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Computers, IEEE Transactions on

Issue 1 • Date Jan. 1986

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  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1986 , Page(s): c1
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    Freely Available from IEEE
  • IEEE Computer Society

    Publication Year: 1986 , Page(s): c2
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    Freely Available from IEEE
  • Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays

    Publication Year: 1986 , Page(s): 1 - 12
    Cited by:  Papers (184)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (3291 KB)  

    A technique for partitioning and mapping algorithms into VLSI systolic arrays is presented in this paper. Algorithm partitioning is essential when the size of a computational problem is larger than the size of the VLSI array intended for that problem. Computational models are introduced for systolic arrays and iterative algorithms. First, we discuss the mapping of algorithms into arbitrarily large... View full abstract»

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  • Testability Conditions for Bilateral Arrays of Combinational Cells

    Publication Year: 1986 , Page(s): 13 - 22
    Cited by:  Papers (31)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (2785 KB)  

    Two sets of conditions are derived that make one- dimensional bilateral arrays of combinational cells testable for single faulty cells. The test sequences are preset and, in the worst case, grow quadratically with the size of the array. Conditions for testability in linear time are also derived. The basic cell can operate at the bit or at the word level. An implementation of FIR filters using (sys... View full abstract»

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  • DFSP: A Data Flow Signal Processor

    Publication Year: 1986 , Page(s): 23 - 33
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (3275 KB)  

    The concept of data flow computing is applied to digital signal processing (DSP). A data flow signal processor (DFSP) architecture is presented. The principles of data flow computing are carefully considered in order to conform with the special properties of DSP. The bus oriented architecture is easily configured to meet various performance requirements. The DFSP architecture is most suitable for ... View full abstract»

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  • A Heuristic for Suffix Solutions

    Publication Year: 1986 , Page(s): 34 - 42
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (2770 KB)  

    The suffix problem has appeared in solutions of recurrence systems for parallel and pipelined machines and more recently in the design of gate and silicon compilers. In this paper we present two algorithms. The first algorithm generates parallel suffix solutions with minimum cost for a given length, time delay, availability of initial values, and fanout. This algorithm generates a minimal solution... View full abstract»

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  • Determining an Optimal Secondary Storage Service Rate for the PASM Control System

    Publication Year: 1986 , Page(s): 43 - 53
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (3339 KB)  

    One class of reconfigurable parallel processing systems is based on the use of a large number of processing elements which can be partitioned into multiple virtual machines. Each virtual machine is controlled by one or more control units. The multiple control units in such a system share a common secondary storage for programs. The control units use paging to transfer programs to their primary mem... View full abstract»

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  • An Enhanced Approximation by Pair-Wise Analysis of Servers for Time Delay Distributions in Queueing Networks

    Publication Year: 1986 , Page(s): 54 - 61
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (2343 KB)  

    An approximation for the distribution of time delays experienced by a customer in a network of queues is presented. Approximate analytical models are necessary since exact solutions are only available for a very restricted class of networks, and are too complex computationally to be viable in practice. Approximations have so far often proved inadequate, particularly for closed networks with first ... View full abstract»

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  • Optimal Bounds for Finding Maximum on Array of Processors with k Global Buses

    Publication Year: 1986 , Page(s): 62 - 64
    Cited by:  Papers (25)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (794 KB)  

    The problem of finding the maximum of a set of values stored one per processor on a two-dimensional array of processors with a time-shared global bus is considered. The algorithm given by Bokhari is shown to be optimal, within a multiplicative constant, for this network and for other d-dimensional arrays. We generalize this model and demonstrate optimal bounds for finding the maximum of a set of v... View full abstract»

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  • The Bidirectional Double Latch (BDDL)

    Publication Year: 1986 , Page(s): 65 - 66
    Cited by:  Papers (3)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (434 KB)  

    This paper describes a new type of shift register latch that is compatible with LSSD. The new latch has the property that information may be shifted in and out of it in two directions: left to right and right to left. View full abstract»

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  • Asynchronous Modular Arbiter

    Publication Year: 1986 , Page(s): 67 - 70
    Cited by:  Papers (4)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (836 KB)  

    A practical N-user arbiter and its implementation are presented in this correspondence. Because of the asynchronous character of its input variables (request signals), the design proposed is asynchronous and keeps in mind the possibility of metastable operations. The structure of the arbiter is very simple and modular. View full abstract»

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  • Deductive Fault Simulation of Internal Faults of Inverter-Free Circuits and Programmable Logic Arrays

    Publication Year: 1986 , Page(s): 70 - 73
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (803 KB)  

    A method for the deductive fault simulation of faults in inverter-free circuits is presented. It is shown that in an inverter-free circuit, fault lists on lines with complementary logic values are disjoint, and fault list calculations can be done by performing fewer set operations compared to conventional gate level deductive simulation. Applications of the method to programmable logic arrays (PLA... View full abstract»

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  • A Note on the Restricted Range Cutting Algorithm

    Publication Year: 1986 , Page(s): 73
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (204 KB)  

    In [1], an algorithm to compute bounds on signal probabilities in VLSI nets is provided. View full abstract»

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  • Systolic Algorithnis for Local Operations on Images

    Publication Year: 1986 , Page(s): 73 - 77
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1141 KB)  

    Local operators, used in many image processing tasks, involve replacing each pixel in an image with a value computed within a local neighborhood of that pixel. Computing such operators at the video rate requires a computing power which is not provided by conventional computers. Though computationally expensive, local operators are highly regular. Thus, a VLSI implementation appears particularly ap... View full abstract»

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  • Global Flow Analysis in Automatic Logic Design

    Publication Year: 1986 , Page(s): 77 - 81
    Cited by:  Papers (21)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1200 KB)  

    This correspondence concerns applications of optimization techniques based on global flow analysis to the automated design of logic. Previous optimization work on logic design has relied primarily on either local transformations on the circuit graph or on the use of two-level Boolean minimization. Our methods involve linear time algorithms which extend the scope of local optimizations to the entir... View full abstract»

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  • The Influence of Masking Phenomenon on Coverage Capability of Single Fault Test Sets in PLA's

    Publication Year: 1986 , Page(s): 81 - 85
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (972 KB)  

    It is relatively easy to generate a complete single contact fault detection test set Tc for a PLA. However such a test set may fail to detect all multiple faults due to the phenomenon of masking. In previous papers attempting to quantitatively predict the multiple fault coverage capability of a single fault detection test set Tc in PLA's, it was proved that every multiple contact fault in an irred... View full abstract»

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  • On the Impossible Class of Faulty Functions in Logic Networks Under Short Circuit Faults

    Publication Year: 1986 , Page(s): 85 - 90
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1365 KB)  

    The important problem of recognizing a priori the class of Boolean functions which are never obtainable from a given combinational network under short circuit faults is almost unexplored, primarily due to lack of understanding of the functional and structural factors that influence the fault behavior in the network. In view of this, a new concept of impossible class of faulty functions (ICFF) is i... View full abstract»

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  • On System Diagnosability in the Presence of Hybrid Faults

    Publication Year: 1986 , Page(s): 90 - 93
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1083 KB)  

    This correspondence deals with the problem of testing the diagnosmbllity of a system in presence of hybrid faults (that is, when some of the units of the system have failed intermittently and some have failed permanently). Presence of intermittent faults can lead to incomplete diagnosis and usually complicates the diagnosis problem in comparison to permanent fault situation. Alternative characteri... View full abstract»

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  • Comments on "The Diogenes Approach to Testable Fault-Tolerant Arrays of Processors"

    Publication Year: 1986 , Page(s): 93
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (273 KB)  

    The above paper1presents an approach to the design of fault- tolerant processor arrays. In Section IV of this paper (related work on fault-tolerant networks) the author criticizes a previously published approach presented by Koren [1] and by Gordon, Koren and Silberman [2]. In [1], an algorithm for structuring a linear array on a rectangular grid of processing elements (PE's), some of w... View full abstract»

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  • Author's Reply2

    Publication Year: 1986 , Page(s): 93 - 94
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (407 KB)  

    Professor Koren's comments on my paper raise a number of points that merit more attention than they typically receive in the literature. View full abstract»

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  • Correction to "Fault-Tolerant Multiprocessor Link and Bus Architectures"

    Publication Year: 1986 , Page(s): 94
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (146 KB)  

    In the above paper1 the following typographical errors should be corrected. View full abstract»

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  • IEEE copyright form

    Publication Year: 1986 , Page(s): 95
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    Freely Available from IEEE
  • IEEE Computer Society Publications

    Publication Year: 1986 , Page(s): 95
    Save to Project icon | Request Permissions | PDF file iconPDF (183 KB)  
    Freely Available from IEEE
  • Information for authors

    Publication Year: 1986 , Page(s): 95
    Save to Project icon | Request Permissions | PDF file iconPDF (203 KB)  
    Freely Available from IEEE

Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org