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IEEE Transactions on Computers

Issue 8 • Aug. 1985

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Displaying Results 1 - 19 of 19
  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1985, Page(s): c1
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  • IEEE Computer Society

    Publication Year: 1985, Page(s): c2
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  • Generation of a Precise Binary Logarithm with Difference Grouping Programmable Logic Array

    Publication Year: 1985, Page(s):681 - 691
    Cited by:  Papers (20)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2753 KB)

    The design algorithm of a differential group programmable logic array (DGPLA) to generate the precise binary logarithm function is suggested. It can reach an optimal condition such that the number of bits in a PLA is minimized, while the error is still kept as small as possible. Thus, the space in the PLA is saved, estimated at only 15.94 percent of the space for a readonly memory (ROM) counterpar... View full abstract»

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  • Retrofitting the VAX-11/780 Microarchitecture for IEEE Floating Point Arithmetic—Implementation Issues, Measurements, and Analysis

    Publication Year: 1985, Page(s):692 - 708
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4752 KB)

    The VAX-11/7801 was designed specifically to implement the VAX architecture. As such, it does not support the IEEE standard for floating point arithmetic. A project was undertaken to provide this support by modifying the 11/780 microarchitecture. Our objective was to produce a microengine that would efficiently execute the VAX instruction set, modified to handle VAX floating point instructions in ... View full abstract»

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  • VLSI Architectures for Computing Multiplications and Inverses in GF(2m)

    Publication Year: 1985, Page(s):709 - 717
    Cited by:  Papers (209)  |  Patents (40)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (6229 KB)

    Finite field arithmetic logic is central in the implementation of Reed-Solomon coders and in some cryptographic algorithms. There is a need for good multiplication and inversion algorithms that can be easily realized on VLSI chips. Massey and Omura [1] recently developed a new multiplication algorithm for Galois fields based on a normal basis representation. In this paper, a pipeline structure is ... View full abstract»

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  • Self-Implicating Structures for Diagnosable Systems

    Publication Year: 1985, Page(s):718 - 723
    Cited by:  Papers (21)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2431 KB)

    In this paper, a new class of diagnosable systems, called tp-self-implicating systems, which is a special case of the well-known tp-diagnosable systems introduced by Preparata et al. [1], is described. If there are no more than tp faulty units and the faults are assumed to be permanent, then the faulty units in a tp-self-implicating system can always be identified using at least one of two straigh... View full abstract»

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  • Square-Rooting Algorithms for High-Speed Digital Circuits

    Publication Year: 1985, Page(s):724 - 733
    Cited by:  Papers (47)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2952 KB)

    Two binary algorithms for the square rooting of a number or of a sum of two numbers are presented. They are based on the classical nonrestoring method. The main difference lies in the replacement of subtractions and additions by a parallel reduction f three summands, which may be positive and negative, to two summands to eliminate the carry propagation. Two of three summands form the successive pa... View full abstract»

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  • Synchronizing Large VLSI Processor Arrays

    Publication Year: 1985, Page(s):734 - 740
    Cited by:  Papers (79)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2719 KB)

    Highly parallel VLSI computing structures consist of many processing elements operating simultaneously. In order for such processing elements to communicate among themselves, some provision must be made for synchronization of data transfer. The simplest means of synchronization is the use of a global clock. Unfortunately, large clocked systems can be difficult to implement because of the inevitabl... View full abstract»

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  • A Fast Serial-Parallel Binary Multiplier

    Publication Year: 1985, Page(s):741 - 744
    Cited by:  Papers (28)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (679 KB)

    A fast serial-parallel (FSP) multiplier design is derived from the carry-save add-shift (CSAS) multiplier structure. The CSAS technique accepts multiplier bits serially (lsb first) and produces outputs serially (lsb first). Multiplication of two n bit unsigned numbers requires 2n clock cycles to complete the process out of which n clocks are used for n-row carry-save additions, and the other n clo... View full abstract»

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  • General Model for Memory Interference in Multiprocessors and Mean Value Analysis

    Publication Year: 1985, Page(s):744 - 751
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1439 KB)

    This correspondence seeks to generalize and clarify the general model for memory interference (GMI) in multiprocessors as proposed by Hoogendoorn. The interference model creates a queueing network where some service centers are FCFS with constant service times; therefore, we also apply the mean value analysis (MVA) approxdmation suggested by Reiser to solve this model. Furthermore, we reduce the c... View full abstract»

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  • Ensuring Fault Tolerance of Phase-Locked Clocks

    Publication Year: 1985, Page(s):752 - 756
    Cited by:  Papers (40)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (976 KB)

    Processors within a real-time multiprocessor system must be synchronized with as little overhead as possible. Although synchronization can be achieved via both software (e.g., interactive convergence and interactive consistency algorithms) and hardware (e.g., multistage synchronizers and phase-locked clocks), phase-locked clocks are most attractive due to their small overheads. View full abstract»

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  • Note on a Proposed Test for Random Number Generators

    Publication Year: 1985, Page(s):756 - 758
    Cited by:  Papers (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (646 KB)

    A recently proposed test for uniform random number generators is based on the mean and variance of the outcome of a sequence of iterations. This note points out that many nonuniform random number generators would pass such a test, and derives an improved test based on the exact distribution of the outcome. View full abstract»

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  • A Totally Self-Checking Error Indicator

    Publication Year: 1985, Page(s):758 - 761
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (884 KB)

    This correspondence presents a totally self-checking error indicator for solving the practical problem of monitoring the TSC checkers. We consider TSC checkers designed for checking coded information (data or address) or periodic signals with tolerable transient failures smaller than a constant time limit T, which depends on the propagation delay of the used logic elements. This circuit provides n... View full abstract»

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  • Verification of Register Transfer Level Parallel Control Sequences

    Publication Year: 1985, Page(s):761 - 765
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1196 KB)

    This correspondence presents a method for proof of correctness of register transfer level (RTL) parallel control sequences that describe hardware behavior. An RTL language endowed with parallel constructs is presented and its semantics is defined. The semantics includes temporal behavior. An assertion-based proof method is presented for verification of parallel control sequences described in this ... View full abstract»

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  • A Symmetric Tree Structure Interconnection Network and its Message Traffic

    Publication Year: 1985, Page(s):765 - 769
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (927 KB)

    A variation of the tree structure interconnection network for the message switching multiprocessor system is presented in this correspondence. It mainly consists of four binary tree structures, pairs of which are touched by their leaf nodes; in addition, there are four nodes which interface with external environments. The proposed network is left-right and top-down symmetric and is planar. Every n... View full abstract»

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  • Interconnection Networks Based on a Generalization of Cube-Connected Cycles

    Publication Year: 1985, Page(s):769 - 772
    Cited by:  Papers (48)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (976 KB)

    A generalization of the cube-connected cycles of Preparata and Vuillemin is described which retains the symmetry of these architectures while allowing for constructions of greater density and of arbitrary degree. These constructions are of a type known as Cayley graphs, and their analysis is greatly facilitated by the applicability of methods from abstract algebra. View full abstract»

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  • Reconfiguration Algorithms for Interconnection Networks

    Publication Year: 1985, Page(s):773 - 776
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (899 KB)

    The correspondence examines the functional relations within a class of multistage interconnection networks. It is known that these networks are not rearrangeable. This fact has led to some research on interconnection network relations. The correspondence deals with one aspect of this research, namely, that of constructing an equivalence map between two interconnection networks. Procedures are give... View full abstract»

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  • IEEE Computer Society Publications

    Publication Year: 1985, Page(s): 776
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  • Information for authors

    Publication Year: 1985, Page(s): 776
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org