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Computers, IEEE Transactions on

Issue 5 • Date May 1985

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Displaying Results 1 - 17 of 17
  • IEEE Transactions on Computers - Table of contents

    Page(s): c1
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  • IEEE Computer Society

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  • A VLSI Design of a Pipeline Reed-Solomon Decoder

    Page(s): 393 - 403
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    A pipeline structure of a transform decoder similar to a systolic array is developed to decode Reed-Solomon (RS) codes. An important ingredient of this design is a modified Euclidean algorithm for computing the error-locator polynomial. The computation of inverse field elements is completely avoided in this modification of Euclid's algorithm. The new decoder is regular and simple, and naturally suitable for VLSI implementation. An example illustrating both the pipeline and systolic array aspects of this decoder structure is given for a (15,9) RS code. View full abstract»

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  • Vector-Reduction Techniques for Arithmetic Pipelines

    Page(s): 404 - 411
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    Vector-reduction arithmetic accepts vectors as inputs and produces scalars as outputs. This class of vector operation forms the basis of many scientific computations, such as inner product and finding the maximum among the vector components. Vector reduction on a pipeline processor demands a feedback connection around the pipeline. Since the output of such a pipeline depends on the previous output, improper control of the feedback input may destroy the benefit from pipelining. Two new vector-reduction techniques are proposed in this paper. In addition to saving reduction time and eliminating intermediate storage (as compared to Kuck's method and Kogge's method), the new methods will greatly simplify the machine-level programming effort needed to implement vector-reduction operations. An interleaved technique is introduced to reduce multiple vectors to corresponding scalars using the same arithmetic pipeline. The pipeline can be fully utilized by interleaving multiple vector-reduction processes. The proposed techniques can be applied to improve the performance of vector-arithmetic pipelines in scientific supercomputers. View full abstract»

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  • On the Rearrangeability of 2(Iog2N) –1 Stage Permutation Networks

    Page(s): 412 - 425
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    For any parallel computer systems which consist of many processing elements and memories, interconnection networks provide communication paths among processing elements and memories. Both the rearrangeability proof and the control algorithm are well known for the Benes network, which is intrinsically symmetric. However, there has been little progress for the case of nonsymmetric networks of similar hardware requirements. View full abstract»

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  • Modeling and Test Generation Algorithms for MOS Circuits

    Page(s): 426 - 433
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    An application of the D-algorithm in generating tests for MOS circuit faults is described. The MOS circuits considered are combinational and acyclic but may contain transmission gates and buses. Tests are generated for both the stuck type faults and the transistor faults (open and short). A logic model is derived for the MOS circuits. In addition to the conventional logic gates, a new type of modeling block is used to represent the "memory" state caused by the "open" transistors. Every fault, whether a stuck type fault or a transistor fault, is represented in the model as a stuck fault at a certain gate input. For generating tests, however, the D-algorithm needs modification. The singular cover and the D-cubes for the new gate include some memory states. To handle the memory state, an initialization procedure has been added to the consistency part of the D-algorithm. The procedure of modeling and test generation is finally extended to transmission gates and buses. View full abstract»

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  • Dynamically Restructurable Fault-Tolerant Processor Network Architectures

    Page(s): 434 - 447
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    A class of novel fault-tolerant multiprocessor networks is proposed. These networks are restructurable in that they can assume different logical configurations to suit different problem environments. More importantly, this restructuriing capability is not altered even after the occurrence of faults. These networks are novel in that they uniquely combine certain desirable features, including self-routing of messages, dynamic reconfigurability, fault-tolerance, the ability to incorporate incremental extension, as well as the capacity to be partitioned with fault-tolerance. What is important about these fault-tolerant features is that they are built-in as an integral part of the design, and not as done traditionally, by means of redundancy. View full abstract»

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  • Wafer-Scale Integration of Systolic Arrays

    Page(s): 448 - 461
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    VLSI technologists are fast developing wafer-scale integration. Rather than partitioning a silicon wafer into chips as is usually done, the idea behind wafer-scale integration is to assemble an entire system (or network of chips) on a single wafer, thus avoiding the costs and performance loss associated with individual packaging of chips. A major problem with assembling a large system of microprocessors on a single wafer, however, is that some of the processors, or cells, on the wafer are likely to be defective. In the paper, we describe practical procedures for integrating "around" such faults. The procedures are designed to minimize the length of the longest wire in the system, thus minimizing the communication time between cells. Although the underlying network problems are NP-complete, we prove that the procedures are reliable by assuming a probabilistic model of cell failure. We also discuss applications of the work to problems in VLSI layout theory, graph theory, fault-tolerant systems, planar geometry, and the probabilistic analysis of algorithms. View full abstract»

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  • On the Performance of Synchronous Multiprocessors

    Page(s): 462 - 466
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    In this correspondence, we study the performance of a multiprocessor in which a crossbar is employed to interconnect p processors to m commonly shared memory modules. A set of nonuniformly distributed probabilities including a probability P(0) which denotes the probability of a processor not generating any request is also employed to illustrate the program behavior, but no distinction is made between processors. Several relations between the average request completion time, the average processor utilization, and the effective memory bandwidth are obtained. One approximation method based on the idea of aggregation is proposed. Its solutions are compared to the exact solution. View full abstract»

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  • Segmented Testing

    Page(s): 467 - 471
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    The fraction of faults detected for a digital network is frequently high for the first few input combinations applied out of a set of test vectors. For on-line testing, there appears to be an advantage to splitting the test into segments which are applied at different times. It is shown that the expected time to error detection and the probability of an undetected double error can be reduced. The amount of reduction is dependent on the shape of the fault coverage curve. This approach may be applicable in fault-tolerant systems. View full abstract»

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  • Integrated-Circuit Logarithmic Arithmetic Units

    Page(s): 475 - 483
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    This correspondence examines integrated-circuit logarithmic arithmetic units which include adders, subtracters, multipliers, and dividers. The design of these arithmetic units is reviewed, and an example arithmetic unit which performs multiplication followed by addition is designed in detail. The design results are used to develop a size and speed comparison of integrated-circuit logarithmic and fixed-point arithmetic units. This comparison is exercised through a video signal processing example. It is concluded from this comparison that logarithmic arithmetic units are smaller than, and as fast as, fixed-point arithmetic units with comparable capabilities in digital signal processing applications characterized by large dynamic range and moderate computational accuracy requirements. Further, this comparison quantitatively illustrates the interaction of digital-signal-processing and integrated-circuit issues in the design of special-purpose digital signal processors. View full abstract»

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  • Systolic Arrays with Embedded Tree Structures for Connectivity Problems

    Page(s): 483 - 484
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    We show how tree structures can be embedded in a one-dimensional systolic array to solve a connectivity problem, the UNION-FIND problem, by a single left-to-right pass of the data through the array. A previous solution, which did not use trees, required a left-to-right pass followed by a right-to-left pass through the array, as well as a more complex program for each cell. View full abstract»

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  • Extending the Scope of Golub's Method Beyond Complex Multiplication

    Page(s): 484 - 487
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    Golub's method of complex multiplication is extended to other contexts such as multiplication with some 2 x 2 matrices and Latin squares. Some applications in further speeding up the FFT or other fast transforms are discussed. View full abstract»

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  • Call for Papers Special Issue on Fault-Tolerant Computing

    Page(s): 488
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  • IEEE Computer Society Publications

    Page(s): 488
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  • Information for authors

    Page(s): 488
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Albert Y. Zomaya
School of Information Technologies
Building J12
The University of Sydney
Sydney, NSW 2006, Australia
http://www.cs.usyd.edu.au/~zomaya
albert.zomaya@sydney.edu.au