IEEE Transactions on Computers

Issue 5 • May 1984

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Displaying Results 1 - 16 of 16
  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1984, Page(s): c1
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  • IEEE Computer Society

    Publication Year: 1984, Page(s): c2
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  • MANIP—A Multicomputer Architecture for Solving Combinatonal Extremum-Search Problems

    Publication Year: 1984, Page(s):377 - 390
    Cited by:  Papers (48)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3889 KB)

    In this paper, we propose and analyze the design of MANIP, a parallel machine for processing nondeterministic polynomial (NP)-hard problems. The most general technique that can be used to solve a wide variety of NP-hard problems on a uniprocessor system, optimally or suboptimally, is the branch-and-bound algorithm. We have adapted and extended branch-and-bound algorithms for parallel processing. T... View full abstract»

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  • A Massive Memory Machine

    Publication Year: 1984, Page(s):391 - 399
    Cited by:  Papers (38)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3287 KB)

    This paper argues the case for a computer with massive amounts of primary storage, on the order of tens of billions of bytes. We argue that such a machine, even with a relatively slow processor, can outperform all other super-computers on memory bound computations. This machine would be simple to program. In addition, it could lead to new and highly efficient programs which traded the available sp... View full abstract»

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  • Line Digraph Iterations and the (d, k) Digraph Problem

    Publication Year: 1984, Page(s):400 - 403
    Cited by:  Papers (120)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1993 KB)

    This paper studies the behavior of the diameter and the average distance between vertices of the line digraph of a given digraph. The results obtained are then applied to the so-called (d, k) digraph problem, that is, to maximize the number of vertices in a digraph of maximum out-degree d and diameter k. By line digraph iterations it is possible to construct digraphs with a number of vertices larg... View full abstract»

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  • A Parallel Algorithm for the Knapsack Problem

    Publication Year: 1984, Page(s):404 - 408
    Cited by:  Papers (24)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2233 KB)

    A time–memory-processor tradeoff for the knapsack problem is proposed. While an exhaustive search over all possible solutions of an n-component knapsack requires T = 0(2n) running time, our parallel algorithm solves the problem in O(2n/2) operations and requires only 0(2n/6) processors and memory cells. It is an improvement over previous time–memory-processor tradeoffs, being the only ... View full abstract»

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  • A Parallel Jacobi Diagonalization Algorthm for a Loop Multiple Processor System

    Publication Year: 1984, Page(s):409 - 413
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2120 KB)

    A parallel algorithm for the solution of the eigen-value problem by the Jacobi method is described. At each step of the algorithm, n/2 off-diagonal elements of the n xn matrix are annihilated simultaneously. Furthermore, because of the regular pattern of interprocessor communication, this algorithm is suitable for efficient implementation on a simple loop multiple processor system. View full abstract»

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  • Pipeline and Parallel-Pipeline FFT Processors for VLSI Implementations

    Publication Year: 1984, Page(s):414 - 426
    Cited by:  Papers (173)  |  Patents (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4652 KB)

    In some signal processing applications, it is desirable to build very high performance fast Fourier transform (FFT) processors. To meet the performance requirements, these processors are typically highly pipelined. Until the advent of VLSI, it was not possible to build a single chip which could be used to construct pipeline FFT processors of a reasonable size. However, VLSI implementations have co... View full abstract»

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  • Optimal Three-Layer Channel Routing

    Publication Year: 1984, Page(s):427 - 437
    Cited by:  Papers (68)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3252 KB)

    In this paper we show that any channel routing problem of density d involving only two-terminal nets can always be solved in the knock-knee mode in a channel of width equal to the density d with three conducting layers. An algorithm is described which produces in time O(n log n) (in its simplest implementation) a layout of n nets with the following properties: 1) it has minimal width d; 2) it can ... View full abstract»

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  • An Improved Min-Cut Algonthm for Partitioning VLSI Networks

    Publication Year: 1984, Page(s):438 - 446
    Cited by:  Papers (194)  |  Patents (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2791 KB)

    Recently, a fast (linear) heuristic for improving min-cut partitions of VLSI networks was suggested by Fiduccia and Mattheyses [6]. In this-paper we generalize their ideas and suggest a class of increasingly sophisticated heuristics. We then show, by exploiting the data structures originally suggested by them, that the computational complexity of any specific heuristic in the suggested class remai... View full abstract»

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  • New Designs for Dense Processor Interconnection Networks

    Publication Year: 1984, Page(s):447 - 450
    Cited by:  Papers (30)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (852 KB)

    Distributed computer systems can be modeled using graph theory to evaluate potential network topologies. A good network from a communication standpoint should have a small diameter because this allows all pairs of processors to communicate quickly. This paper presents a new construction method for interconnection networks, which is a generalization of the chordal ring networks of Arden and Lee. Th... View full abstract»

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  • A Loop-Structured Switching Network

    Publication Year: 1984, Page(s):450 - 455
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1364 KB)

    This paper describes a novel loop-structured switching network (LSSN) intended for highly parallel processing architectures. With L loops, it can connect up to N = L* log2 L pairs of transmitting and receiving devices using only N/2 two-by-two switching elements; thus, it is very cost-effective in terms of its component count. Its topology resembles that of the indirect binary n-cube network, but ... View full abstract»

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  • Area-Time Optimal Fast Implementation of Several Functions in a VLSI Model

    Publication Year: 1984, Page(s):455 - 462
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1489 KB)

    Area and computation time are considered to be important measures with which VLSI circuits are evaluated. In this paper, the area-time complexity for nontrivial n-input m-output Boolean functions, such as a decoder and an encoder, is studied with a model similar to Brent-Kung's model. A lower bound on area-time-product (ATαaα.≥1) for these functions is shown: for example, AT&#... View full abstract»

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  • Exponential and Logarithm by Sequential Squaring

    Publication Year: 1984, Page(s):462 - 464
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (524 KB)

    A simple scheme is presented for computing the exponential of a floating point number using only shift, add, and multiply instructions. The algorithm involves no range reduction and handles overflow and underflow conditions automatically. It can be used to provide a result of any desired accuracy, provided only that sufficient precision is used during the calculation. The basic algorithm and three... View full abstract»

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  • IEEE Computer Society Publications

    Publication Year: 1984, Page(s): 464
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    Freely Available from IEEE
  • Information for authors

    Publication Year: 1984, Page(s): 464
    Request permission for commercial reuse | PDF file iconPDF (235 KB)
    Freely Available from IEEE

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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org