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IEEE Transactions on Computers

Issue 4 • April 1984

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Displaying Results 1 - 19 of 19
  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1984, Page(s): c1
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  • IEEE Computer Society

    Publication Year: 1984, Page(s): c2
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  • A Matrix Formalism for Asynchronous Implementation of Algorithms

    Publication Year: 1984, Page(s):289 - 300
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3019 KB)

    We show that well-known instructions such as if then else, fork, join, while do, can be represented as row matrices or column-matrices. We define a matrix-instruction which encompasses and generalizes the above instructions. This instruction provides us with a compact tool for describing algorithms and for synthesizing them in synchronous and asynchronous structures. We show, e.g., that the synthe... View full abstract»

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  • A Computer Aided Procedure for Performing Static Loading Validation of Digital Logic Systems

    Publication Year: 1984, Page(s):301 - 313
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3756 KB)

    A logic network is modeled with logic elements and a set of junctions formed by the interconnection of logic element pins. Electrical models for logic element pins are developed that include appropriate current and voltage parameters, and a consistent set of nomenclature for these parameters is introduced. An algorithm is then presented that can be used to determine the ability of ap element pin t... View full abstract»

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  • Fault-Tolerant 256K Memory Designs

    Publication Year: 1984, Page(s):314 - 322
    Cited by:  Papers (15)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (5421 KB)

    A series of designs for a 256K memory are presented which integrate error-correcting coding into the memory organization. Starting from a simple single-error correcting product code, the successive designs explore trade-offs in coding efficiency, access delay, and complexity of communication and computation. In the most powerful design, all the 256K bits are organized so that they form a codeword ... View full abstract»

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  • Generalized Hypercube and Hyperbus Structures for a Computer Network

    Publication Year: 1984, Page(s):323 - 333
    Cited by:  Papers (493)  |  Patents (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3106 KB)

    A general class of hypercube structures is presented in this paper for interconnecting a network of microcomputers in parallel and distributed environments. The interconnection is based on a mixed radix number system and the technique results in a variety of hypercube structures for a given number of processors N, depending on the desired diameter of the network. A cost optimal realization is obta... View full abstract»

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  • Multidimensional Height-Balanced Trees

    Publication Year: 1984, Page(s):334 - 343
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3001 KB)

    A new multidimensional balanced tree structure is presented for the efficient management of multidimensional data. It is shown that the data structure can be used to manage a set of n k-dimensional records or data items such that the records can be searched or updated in O(log2 n) + k time, which is optimal. The data structure is a multidimensional generalization of the height-balanced trees and r... View full abstract»

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  • A Very Fast Parallel Processor

    Publication Year: 1984, Page(s):344 - 350
    Cited by:  Papers (38)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2399 KB)

    A parallel processor specially designed for an important problem in theoretical physics is described. The final device will contain 256 nodes running in lock-step in a SIMD mode with a computational power of 4 billion 22-bit floating point operations per second. Each node is controlled by an Intel 80286/287 microprocessor, contains 160K bits of memory and has a pipelined, microprogrammable arithme... View full abstract»

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  • A Stochastic Optimization Algorithm Minimizing Expected Flow Times on Uniforn Processors

    Publication Year: 1984, Page(s):351 - 356
    Cited by:  Papers (24)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2326 KB)

    First Page of the Article
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  • Systolic Multipliers for Finite Fields GF(2m)

    Publication Year: 1984, Page(s):357 - 360
    Cited by:  Papers (120)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1828 KB)

    Two systolic architectures are developed for performing the product–sum computation AB + C in the finite field GF(2m) of 2melements, where A, B, and C are arbitrary elements of GF(2m). The first multiplier is a serial-in, serial-out one-dimensional systolic array, while the second multiplier is a parallel-in, parallel-out two-dimensional systolic array. The f... View full abstract»

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  • Systolic Algorithms for String Manipulations

    Publication Year: 1984, Page(s):361 - 364
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (933 KB)

    One-and two-dimensional pattern matching oriented systolic array processors are presented that support, respectively, the detection of all repetitions in a string x and the statistics of all substrings of x with and without overlap. The time is linear in the length of x in both applications, whereas the number of processors is linear and quadratic, respectively. View full abstract»

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  • A Representation of Hypergraphs in the Euclidean Space

    Publication Year: 1984, Page(s):364 - 367
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (727 KB)

    This paper introduces a graph space that shows concisely the relative weights among combinations of vertices of a given hypergraph. (A hypergraph is a graph in which one edge may connect two or more vertices.) The hypergraph is represented by a collection of points in graph space such that the distance between vertices in graph space reflects the weights of the edges between vertices of the origin... View full abstract»

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  • The Gamma Network

    Publication Year: 1984, Page(s):367 - 373
    Cited by:  Papers (69)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1331 KB)

    The Gamma network is an interconnection network connecting N = 2n inputs to N outputs. It is a multistage network with N switches per stage, each of which is a 3 input, 3 output crossbar. The stages are linked via "power of two" and identify connections in such a way that redundant paths exist between the input and output terminals. In this network, a path from a source to a destination may be rep... View full abstract»

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  • Limitations on Carry Lookahead Networks

    Publication Year: 1984, Page(s):373 - 374
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (494 KB)

    The fan-in and fan-out limitations imposed by specific gate circuits force corresponding limits-upon the sizes of carry lookahead circuits fabricated from those gates. The relationships between those limits are derived, providing simple formulae that can be used by designers seeking to fabricate fast combinational binary adders. View full abstract»

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  • Benchmarks on Japanese and American Supercomputers—Preliminary Results

    Publication Year: 1984, Page(s): 374
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (274 KB)

    A partial summary of preliminary benchmark results on Japanese and American supercomputers is given. While the results indicate similar scalar capabilities between the Fujitsu VP-200 supercomputer and the one-CPU XMP, they give the Fujitsu VP-200 a clear edge over the one-CPU XMP in vector performance. View full abstract»

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  • Correction to "A Hardware Hashing Scheme in the Design of a Multiterm String Comparator"

    Publication Year: 1984, Page(s): 375
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  • Call for Papers Special Issue on Sorting

    Publication Year: 1984, Page(s): 376
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  • IEEE Computer Society Publications

    Publication Year: 1984, Page(s): 376
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  • Information for authors

    Publication Year: 1984, Page(s): 376
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org