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IEEE Transactions on Computers

Issue 2 • Date Feb. 1984

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Displaying Results 1 - 14 of 14
  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1984, Page(s): c1
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    Freely Available from IEEE
  • IEEE Computer Society

    Publication Year: 1984, Page(s): c2
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  • Design and Evaluation of a Fault-Tolerant Multiprocessor Using Hardware Recovery Blocks

    Publication Year: 1984, Page(s):113 - 124
    Cited by:  Papers (25)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3679 KB)

    In this paper we consider the design and evaluation of a fault-tolerant multiprocessor with a rollback recovery mechanism. View full abstract»

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  • Dynamic Characteristics of Loops

    Publication Year: 1984, Page(s):125 - 132
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2672 KB)

    Loops are directly defined on an instruction execution string rather than on a directed graph model of a program derived from the source code. A simple efficient algorithm to find the loops and subloops thus defined is presented. View full abstract»

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  • Finding Maximum on an Array Processor with a Global Bus

    Publication Year: 1984, Page(s):133 - 139
    Cited by:  Papers (48)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2477 KB)

    The problem of finding the maximum of a set of values stored one per processor on an n X n array of processors is analyzed. The array has a time-shared global bus in addition to conventional processor-processor links. A two-phase algorithm for finding the maximum is presented that uses conventional links during the first phase and the global bus during the second. This algorithm is faster than alg... View full abstract»

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  • A VLSI-Based I/O Formatting Device

    Publication Year: 1984, Page(s):140 - 149
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4715 KB)

    At the present time substantial software, memory, and CPU cycle penalties are incurred in bridging the semantic gap between high-level language formatted output statements and I/O device capabilities. Because of this gap and in response to the rapidly expanding capability of VLSI microelectronic circuits, a dedicated I/O processor is proposed to off-load the inherent conversion and formatting task... View full abstract»

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  • Performance Evaluation of the Computer Network Dynamic Congestion Table Algorthm

    Publication Year: 1984, Page(s):150 - 159
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2806 KB)

    A comparison of the performance of the Dynamic Congestion Table (DCT) Algorithm, a computer network congestion control algorithm's delay table entry generation subalgorithm, is made here with a Pascal implementation of the present ARPANET SPF Algorithm (infinite buffer). The parameters of global throughput, delay, and power versus load are evaluated for 10 and 20 node sections of the ARPANET, usin... View full abstract»

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  • A Switch-Level Model and Simulator for MOS Digital Systems

    Publication Year: 1984, Page(s):160 - 177
    Cited by:  Papers (199)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (5019 KB)

    The switch-level model describes the logical behavior of digital systems implemented in metal oxide semiconductor (MOS) technology. In this model a network consists of a set of nodes connected by transistor "switches" with each node having a state 0, 1, or X (for invalid or uninitialized), and each transistor having a state "open," "closed," or "indeterminate." Many characteristics of MOS circuits... View full abstract»

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  • Architecture for VLSI Design of Reed-Solomon Decoders

    Publication Year: 1984, Page(s):178 - 189
    Cited by:  Papers (21)  |  Patents (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2755 KB)

    In this paper, the known decoding procedures for Reed-Solomon (RS) codes are modified to obtain a repetitive and recursive decoding technique which is suitable for VLSI implementation and pipelining. The chip architectures of two basic building blocks for VLSI RS decoder systems are then presented. It is shown that a VLSI RS decoder has the potential advantage of achieving a high decoding speed th... View full abstract»

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  • Families of Fixed Degree Graphs for Processor Interconnection

    Publication Year: 1984, Page(s):190 - 194
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1101 KB)

    A construction is presented which, given a fixed undirected graph of low degree and small average path length, yields an infinite sequence of low diameter graphs of increasing order and fixed degree. As examples of the construction, infinite sequences of low diameter graphs are presented with degrees in the range 3 to 30. Expressed as a function of the order of the graphs, the degree 3 sequence ha... View full abstract»

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  • Sequential Fault Diagnosis of Modular Systems

    Publication Year: 1984, Page(s):194 - 197
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (834 KB)

    In this correspondence, we present an algorithm based on information theoretic concepts for the design of efficient sequential fault diagnosis experiments for permanent faults in modular systems. View full abstract»

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  • Reliability Evaluation of Fault-Tolerant Systems—Effect of Variability in Failure Rates

    Publication Year: 1984, Page(s):197 - 200
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (821 KB)

    In this correspondence models for the variation in system reliability due to uncertainty in failure rate estimation are developed. Two techniques are proposed. The first is exact and is based on the complete distribution of the failure rate. The second is an approximation and employs only the first and second moments. The application of these models in reliability analysis is then discussed and il... View full abstract»

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  • IEEE Computer Society Publications

    Publication Year: 1984, Page(s): 200
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  • Information for authors

    Publication Year: 1984, Page(s): 200
    Request permission for commercial reuse | PDF file iconPDF (233 KB)
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org