By Topic

IEEE Transactions on Computers

Issue 11 • Date Nov. 1984

Filter Results

Displaying Results 1 - 19 of 19
  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1984, Page(s): c1
    Request permission for commercial reuse | PDF file iconPDF (415 KB)
    Freely Available from IEEE
  • IEEE Computer Society

    Publication Year: 1984, Page(s): c2
    Request permission for commercial reuse | PDF file iconPDF (179 KB)
    Freely Available from IEEE
  • Guest Editors' Introduction Parallel Processing

    Publication Year: 1984, Page(s):949 - 951
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2972 KB)

    AS we approach the limits of how much a single processor's speed can be increased through advances in technology, there is no question that parallelism will be the key to building tomorrow's fastest, mostpowerful computers. Current parallel processing studies demonstrate that parallelism has the potential to provide solutions to a wide range of computationally intensive problems. Nonetheless, at a... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • List of referees

    Publication Year: 1984, Page(s): 951
    Request permission for commercial reuse | PDF file iconPDF (1172 KB)
    Freely Available from IEEE
  • Modular Matrix Multiplication on a Linear Array

    Publication Year: 1984, Page(s):952 - 958
    Cited by:  Papers (29)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2515 KB)

    A matrix multiplication algorithm on a linear array of processing elements is described. The local storage required by the processing elements and the I/O bandwidth required to drive the array are both constants that are independent of the sizes of the matrices being multiplied. The algorithm is therefore modular, that is, arbitrarily large matrices can be multiplied on a large array built by casc... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Improvement Algorithms for Semijoin Query Processing Programs in Distributed Database Systems

    Publication Year: 1984, Page(s):959 - 967
    Cited by:  Papers (29)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3012 KB)

    The problem of optimal query processing in distributed database systems was shown to be NP-hard. This means that heuristic algorithms are necessary to solve the query processing problem. In this paper, we describe algorithms to improve the solutions generated by heuristics. We have identified four properties which optimal semijoin programs for processing tree queries have to satisfy. A semijoin pr... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Measuring the Parallelism Available for Very Long Instruction Word Architectures

    Publication Year: 1984, Page(s):968 - 976
    Cited by:  Papers (66)  |  Patents (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3377 KB)

    Long instruction word architectures, such as attached scientific processors and horizontally microcoded CPU's, are a popular means of obtaining code speedup via fine-grained parallelism. The falling cost of hardware holds out the hope of using these architectures for much more parallelism. But this hope has been diminished by experiments measuring how much parallelism is available in the code to s... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Efficient Internode Communications in Reconfigurable Binary Trees

    Publication Year: 1984, Page(s):977 - 990
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2355 KB)

    This paper discusses efficient communication algorithms for multicomputer networks organized as reconfigurable binary trees. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Packet Switching Networks for Multiprocessors and Data Flow Computers

    Publication Year: 1984, Page(s):991 - 1003
    Cited by:  Papers (25)  |  Patents (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3544 KB)

    Most packet switched multistage networks have been proposed to use a unique path between any source and destination. We propose to add a few extra stages to create multiple paths between any source and destination. Connection principles of such multipath networks for packet switching are presented. Performance of such networks is analyzed for possible use in multiprocessor systems or in data flow ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Closed-Form Solution for the Perfornance Analysis of Multiple-Bus Multiprocessor Systems

    Publication Year: 1984, Page(s):1004 - 1012
    Cited by:  Papers (41)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2886 KB)

    A closed-form solution for the performance analysis of multiple-bus multiprocessor systems is presented. A Markovian queueing network model has been developed to investigate the effects of memory and bus contentions on the system performance. The symmetrical structure of the Markov chains of the queueing model makes it possible to demonstrate that the local balance is satisfied. Consequently, the ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Instruction Issue Logic in Pipelined Supercomputers

    Publication Year: 1984, Page(s):1013 - 1022
    Cited by:  Papers (36)  |  Patents (94)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3221 KB)

    Basic principles and design tradeoffs for control of pipelined processors are first discussed. We concentrate on register-register architectures like the CRAY-1 where pipeline control logic is localized to one or two pipeline stages and is referred to as "instruction issue logic." Design tradeoffs are explored by giving designs for a variety of instruction issue methods that represent a range of c... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Practical Multiprocessor Scheduling Algorithms for Efficient Parallel Processing

    Publication Year: 1984, Page(s):1023 - 1029
    Cited by:  Papers (245)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3029 KB)

    First Page of the Article
    View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Fast Execution of Loops with IF Statements

    Publication Year: 1984, Page(s):1030 - 1033
    Cited by:  Papers (7)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (842 KB)

    A parallel method of execution for a certain class of loops containing IF statements is described. We replace a given loop by an equivalent set of five loops, four of which are vectorizable; the fifth loop is executed in hardware as a Boolean recurrence. The proposed architecture handles all loops that produce recurrences with order ≤m, a hardware parameter. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Memory Interference Models with Variable Connection Time

    Publication Year: 1984, Page(s):1033 - 1038
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1185 KB)

    This correspondence develops two discrete memory interference models. These models, the equivalent rate model and the Markov chain model, provide for variable connection times between processors and memories if these times can be characterized by a discrete random variable X. The equivalent rate model, which is the simpler, requires only the first moment of X, while the Markov chain model requires... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An Efficient Implementation of Search Trees on [lg N + 1] Processors

    Publication Year: 1984, Page(s):1038 - 1041
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1037 KB)

    A scheme for maintaining a balanced search tree on γlg N + 1γparallel processors is described. The scheme is almost fully pipelined: γlg N + 1γ/2 search, insert, and delete operations may run concurrently. Each processor executes 0(1) instructions of a top-down 2-3-4 tree manipulation algorithm before passing the operation along to the next processor in the pipeline. Thus, the ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Multiprocessor Architecture for Generating Fractal Surfaces

    Publication Year: 1984, Page(s):1041 - 1045
    Cited by:  Papers (4)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1284 KB)

    Fractal surfaces have recently been shown to be a useful model for generating images of terrain in computer graphicS. Unfortunately, the generation of fractal images is very costly in CPU time. A multiprocessor architecture is described which takes advantage of the parallelism inherent in fractals to speed the generation of images. The performance of the processing array is analyzed along with the... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The Performance of Multimicrocomputer Networks Supporting Dynamic Workloads

    Publication Year: 1984, Page(s):1045 - 1048
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (875 KB)

    Because a group of interconnected microcomputers may not share any globally addressable memory, it is crucial that a multimicrocomputer interconnection network capable of efficiently supporting message passing be found. Using task precedence graphs to represent the time varying behavior of parallel computations, both the behavior of interconnection networks under varying workloads and the feasibil... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • IEEE Computer Society Publications

    Publication Year: 1984, Page(s): 1048
    Request permission for commercial reuse | PDF file iconPDF (182 KB)
    Freely Available from IEEE
  • Information for authors

    Publication Year: 1984, Page(s): 1048
    Request permission for commercial reuse | PDF file iconPDF (221 KB)
    Freely Available from IEEE

Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org