IEEE Transactions on Computers

Issue 10 • Oct. 1984

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  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1984, Page(s): c1
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  • IEEE Computer Society

    Publication Year: 1984, Page(s): c2
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  • Synthesis and Asynchronous Implementation of Algorithms Using a Generalized P-Function Concept

    Publication Year: 1984, Page(s):861 - 868
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1265 KB)

    A formalism has been introduced for program description and synthesis, namely the matrix description of instructions. In this paper we put that formalism to work by associating with it computation methods based on a generalized P-function concept. Algorithms are derived for the optimal implementation of programs in asynchronously organized structures. View full abstract»

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  • Poolpo—A Pool of Processors for Process Control Applications

    Publication Year: 1984, Page(s):869 - 878
    Cited by:  Papers (13)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (3330 KB)

    The Poolpo of Brown, Boveri & Company (BBC) Research Center is an experimental multiprocessor that was built to test the validity of the concept of a pool of processors in the process control field. It is a tightly coupled multiprocessor which consists of 9 processors (LSI-1l) sharing a common memory by means of a high-speed bus (an early prototype of the IEEE P896 backplane bus). The processo... View full abstract»

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  • Input Variable Assignment and Output Phase Optimization of PLA's

    Publication Year: 1984, Page(s):879 - 894
    Cited by:  Papers (92)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (3218 KB)

    A PLA minimization system having the following features is presented: 1) minimization of both two-level PLA's and PLA's with two-bit decoders; 2) optimal input variable assignment to the decoders; 3) optimal output phase assignment; and 4) essential prime implicants detection without generating all the prime implicants. View full abstract»

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  • Task Preloading Schemes for Reconfigurable Parallel Processing Systems

    Publication Year: 1984, Page(s):895 - 905
    Cited by:  Papers (5)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (3314 KB)

    One class of reconfigurable parallel processing systems is based on the use of a large number of processing elements where each processing element consists of a processor and a primary memory. To efficiently employ the processing elements, it is desirable to overlap the operation of the secondary storage with computations being performed by the processors. Due to the dynamically reconfigurable arc... View full abstract»

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  • The VLSI Implementation of a Reed—Solomon Encoder Using Berlekamp's Bit-Serial Multiplier Algorithm

    Publication Year: 1984, Page(s):906 - 911
    Cited by:  Papers (20)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (3185 KB)

    Berlekamp has developed for the California Institute of Technology Jet Propulsion Laboratory (JPL) a bit-serial multiplication algorithm for the encoding of Reed-Solomon (RS) codes, using a dual basis over a Galois field. The conventional RS encoder for long codes often requires lookup tables to perform multiplication of two field elements. Berlekamp's algorithm requires only shifting and EXCLUSIV... View full abstract»

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  • Two Designs of a Fault-Tolerant Clocking System

    Publication Year: 1984, Page(s):912 - 919
    Cited by:  Papers (23)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1892 KB)

    Two designs of a fault-tolerant clocking system are described: a time-discrete design based on autonomous oscillators and a time-continuous design based on voltage-controlled oscillators. In both designs the system consists of a number of identical modules producing as many mutually synchronous binary clock signals. The system is fault-tolerant in that if at most f modules fail, the remaining modu... View full abstract»

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  • A Robust Matrix-Multiplication Array

    Publication Year: 1984, Page(s):919 - 922
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (881 KB)

    Matrix multiplication algorithms have been proposed for VLSI array processors. Random defects in the silicon wafer and fabrication errors render processors and data paths in the array faulty, and may cause the algorithm to fail despite a significant number of nonfaulty processors. This correspondence presents a robust VLSI array processor for matrix multiplication. The array is driven by a host co... View full abstract»

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  • Dynamic Memory Interconnections for Rapid Access

    Publication Year: 1984, Page(s):923 - 927
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1138 KB)

    In this correspondence we consider a model for dynamic memories that are characterized by small cell fan-out and a small number of I/O ports. Many schemes have been proposed in the literature to interconnect dynamic memory cells. These usually exhibit a tradeoff between random and block access times. We propose a scheme that combines the interconnection scheme of a previous work with the idea of i... View full abstract»

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  • Residue Number System Truth-Table Look-Up Processing—Moduli Selection and Logical Minimization

    Publication Year: 1984, Page(s):927 - 931
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1131 KB)

    Truth table look-up processing using binary coded residue numbers is investigated for full-precision addition and multiplication for implementations using either electronic or optical technologies. The logically minimized numbers of input combinations needed for each operation are presented for moduli 2-23. The moduli sets that require the minimum number of reference patterns are determined for ad... View full abstract»

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  • External Sorting in VLSI

    Publication Year: 1984, Page(s):931 - 934
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (885 KB)

    The problem of sorting n elements using VLSI chips that can sort only q(q < n) elements at a time is considered. The proposed VLSI chip consists of a mesh of trees. Two classical algorithms, i.e., merge sort and bitonic sort, are modified to efficiently solve the external sorting problem using this chip. View full abstract»

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  • An Analysis of the Use of Rademacher&#8211;Walsh Spectrum in Compact Testing

    Publication Year: 1984, Page(s):934 - 937
    Cited by:  Papers (30)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (645 KB)

    Earlier approaches to random compact testing use a random pattern generator which depends on the combinational function under test and a circuit signature which remains the same independent of the circuit. In this correspondence we analyze the performance of a new scheme in which the pattern generator is simple and independent of the function being tested but the circuit signature is chosen to be ... View full abstract»

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  • The Complexity of Horizontal Word Encoding in Microprogrammed Machines

    Publication Year: 1984, Page(s):938 - 939
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (474 KB)

    We consider the complexity of the problem of encoding microoperations into the fields of a control word on a horizontally microprogrammed machine, and show it to be NP-complete. The major result of this correspondence is a formalization of the microinstruction encoding problem, which makes the complexity argument straightforward. View full abstract»

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  • Routing Algorithms for Cellular Interconnection Arrays

    Publication Year: 1984, Page(s):939 - 942
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (731 KB)

    The paper describes an algebraic model which provides a means for realizing an arbitrary permutation through various cellular-array-type networks. The model views a cellular array as an ordered set of transposition maps where each transposition corresponds to a permutation cell of the array. A permutation realizable by such an array is then expressed as a composition of the transpositions where th... View full abstract»

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  • Diagnosis in the Presence of Known Faults

    Publication Year: 1984, Page(s):943 - 947
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1132 KB)

    Diagnosis of an entire system when known faults are present and diagnosis of particular faults in the system when known faults are present are two diagnosis problems that are relevant to computer systems that are reconfigurable and employ distributed control. These problems are formalized, and a diagnostic model based on a model of Russell and Kime is used to analyze the ability of a system to dia... View full abstract»

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  • Comments on "Fault Diagnosis of MOS Combinational Networks"

    Publication Year: 1984, Page(s): 947
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (180 KB)

    This correspondence points out that the scope of application of the matrix model for MOS complex gates proposed by El-ziq and Su1does not cover general structures of this type. Also, an example is given to show that a complete detection test set for single stuck-at faults may not be able to detect all multiple faults in a fanout-free and irredundant MOS complex gate. View full abstract»

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  • Call For Papers

    Publication Year: 1984, Page(s): 948
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  • IEEE Computer Society Publications

    Publication Year: 1984, Page(s): 948
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  • Information for authors

    Publication Year: 1984, Page(s): 948
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org