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IEEE Transactions on Computers

Issue 9 • Date Sept. 1983

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Displaying Results 1 - 19 of 19
  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1983, Page(s): c1
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  • IEEE Computer Society

    Publication Year: 1983, Page(s): c2
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  • Automated Design of Multiple-Valued Logic Circuits by Automatic Theorem Proving Techniques

    Publication Year: 1983, Page(s):785 - 798
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3476 KB)

    This paper describes a method for the automatic synthesis of multiple-valued combinational logic circuits using automatic theorem proving techniques. Logic design of multiple-valued circuits is considerably more complex than binary design because of the associated combinatorial explosion. Two general approaches which can be taken in axiomatizing the environment of combinational logic design in mul... View full abstract»

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  • Load Redistribution Under Failure in Distributed Systems

    Publication Year: 1983, Page(s):799 - 808
    Cited by:  Papers (22)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2818 KB)

    In order to implement a distributed system with fail-soft capabilities it is necessary to specify algorithms which redistribute the work load of a failed processor to the remaining good processors. This paper develops a general model to analyze the behavior of these algorithms in a distributed system. Such algorithms should be used with caution as they have the capability of making the entire syst... View full abstract»

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  • An Algebraic Model of Fault-Masking Logic Circuits

    Publication Year: 1983, Page(s):809 - 825
    Cited by:  Papers (6)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4759 KB)

    In this paper, an algebraic model of fault-masking logic (FML) circuits, assuming bitwise logical operations and a separate single-valued coding system is presented. From this model, the neccessary and sufficient conditions to construct FML circuits are derived, and the error-propagating and error-correcting characteristics of such FML circuits are defined in terms of a Boolean vector algebra and ... View full abstract»

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  • Mesh-Connected Computers with Broadcasting

    Publication Year: 1983, Page(s):826 - 830
    Cited by:  Papers (95)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2208 KB)

    We consider the effects of augmenting an arbitrary mesh-connected computer with a second communication system called broadcasting. In broadcasting, a processor sends a value to all the other processors simultaneously, taking unit time, with the restriction that only one broadcast occurs at any one time. We show that this significantly decreases the time to do sample problems such as semigroup calc... View full abstract»

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  • A Theory of Totally Self-Checking System Design

    Publication Year: 1983, Page(s):831 - 844
    Cited by:  Papers (25)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3812 KB)

    A totally self-checking digital system uses error detecting codes at subsystem interfaces to detect faults before they can lead to harmful undetected errors. This paper develops a formal model for studying totally self-checking systems. View full abstract»

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  • Optimal Wiring of Movable Terminals

    Publication Year: 1983, Page(s):845 - 858
    Cited by:  Papers (39)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3355 KB)

    In this paper we consider the problem of local wiring in a VLSI chip. The problem is one of interconnecting two sets of terminals, one set on each side of a wiring channel, in accordance with a given interconnection pattern, and to accomplish this while minimizing some objective function. We make the further assumption that the terminals are not rigidly positioned and can be "moved" provided that ... View full abstract»

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  • Dynamic Profile of Instruction Sequences for the IBM System/370

    Publication Year: 1983, Page(s):859 - 861
    Cited by:  Papers (8)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (740 KB)

    Instruction mixes such as the Gibson mix have been used for a long time as workload models for CPU's. However, since an instruction mix does not indicate the order of instruction execution, it is not suitable for the performance evaluation of advanced computers which employ pipelining. Instruction sequences are proposed as a generalization of instruction mixes. The instruction representation does ... View full abstract»

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  • Optimality of a Two-Phase Strategy for Routing in Interconnection Networks

    Publication Year: 1983, Page(s):861 - 863
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (643 KB)

    It is shown that for d-way shuffle graphs all oblivious algorithms for realizing permutations in logarithmic time send packets along routes twice as long as the diameter of the graph. This confirms the optimality of the strategy that sends packets to random nodes in a first phase and to the correct destinations in the second. For the shuffle-exchange graph the corresponding route length is shown t... View full abstract»

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  • On the Minimization of Wordwidth in the Control Memory of a Microprogrammed Digital Computer

    Publication Year: 1983, Page(s):863 - 868
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1289 KB)

    This paper describes a new method for reducing the wordwidth in the control memory of a microprogrammed digital computer. The method requires the computation of maximal compatibility classes (MCC's) of only a subset of subcommands unlike the existing methods in which MCCs of the entire set of subcommands are used. An algorithm has been given to obtain a near minimal solution by appropriate groupin... View full abstract»

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  • Representing the Effect of Instruction Prefetch in a Microprocessor Performance Model

    Publication Year: 1983, Page(s):868 - 872
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1015 KB)

    The implementation of variable addressing and block structure has a substantial influence on the global system performance. One model dederibes this influence as a product of program statistical, architectural and technological parameters, but only for sequential processors. In this correspondence we adapt this model to processors with an instrution prefetch pipeline. An upper and lower bound for ... View full abstract»

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  • Memory Package Error Detection and Correction

    Publication Year: 1983, Page(s):872 - 874
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (704 KB)

    Single error correcting-double error detecting (SEC-DED) codes have been successfully used in computer memories for reliability. In the present-day technology of very large scale integration storage arrays bit error correction as well as byte error detection/byte error correction become extremely important. We devise here classes of cyclic codes with generator of the form (xb -1) p(x) for some sui... View full abstract»

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  • A Parallel Architecture for Digital Filtering Using Fermat Number Transforms

    Publication Year: 1983, Page(s):874 - 877
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (750 KB)

    In this correspondence, a parallel architecture is developed to compute the linear convolution of two sequences of arbitrary lengths using the Fermat number transform (FNT). In particular, a pipeline structure is designed to compute a 128-point FNT. In this FNT, only additions and bit rotations are required. View full abstract»

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  • Correction to "Optimal Query Processing for Distributed Database Systems"

    Publication Year: 1983, Page(s): 878
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (284 KB)

    In the above paper1, Theorem 1 is not true in general. The purpose of Theorem 1 was to reduce the number of feasible query trees by determining the optimal positions of unary operations in a given query tree. In fact, Theorem I is true only if the processing cost of a unary operation is independent of the volume of input data. View full abstract»

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  • On a Bit-Serial Input and Bit-Serial Output Multiplier

    Publication Year: 1983, Page(s):878 - 880
    Cited by:  Papers (19)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (655 KB)

    A recent paper by Chen and Willoner [1] forwarded a bit-sequential input and output (LSBfirst) multiplier for positive numbers. This multiplier for n-bit operands requires 2n clocks and 2n number of five-input adder modules. In this correspondence, after a brief discussion on the different claims made by the authors of [1] and their limitations, we show that this multiplier can be realized with on... View full abstract»

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  • Acknowledgment of Prior Work

    Publication Year: 1983, Page(s): 880
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    First Page of the Article
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  • IEEE Computer Society Publications

    Publication Year: 1983, Page(s): 880
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  • Compsac83

    Publication Year: 1983, Page(s): 880
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org