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Computers, IEEE Transactions on

Issue 8 • Date Aug. 1983

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Displaying Results 1 - 21 of 21
  • IEEE Transactions on Computers - Table of contents

    Page(s): c1
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    Freely Available from IEEE
  • IEEE Computer Society

    Page(s): c2
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    Freely Available from IEEE
  • The Bottomn-Left Bin-Packing Heuristic: An Efficient Implementation

    Page(s): 697 - 707
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    We study implementations of the bottom-left heuristic for two-dimensional bin-packing. To pack N rectangles into an infinite vertical strip of fixed width, the strategy considered here places each rectangle in turn as low as possible in the strip in a left-justified position. For reasons of simplicity and good performance, the bottom-left heuristic has long been a favorite in practical applications; however, the best implementations found so far require a number of steps O(N3). In this paper, we present an implementation of the bottom-left heuristic which requires linear space and quadratic time. The algorithm is fairly practical, and we believe that even for relatively small values of N, it gives the most efficient implementation of the heuristic, to date. It proceeds by first determining all the possible locations where the next rectangle can fit, then selecting the lowest of them. It is optimal among all the algorithms based on this exhaustive strategy, and its generality makes it adaptable to different packing heuristics. View full abstract»

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  • Reduction of Connections for Multibus Organization

    Page(s): 707 - 716
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    The multibus interconnection network is an attractive solution for connecting processors and memory modules in a multiprocessor with shared memory. It provides a throughput which is intermediate between the single bus and the crossbar, with a corresponding intermediate cost. View full abstract»

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  • Stability and Performance of the R-Aloha Packet Broadcast System

    Page(s): 717 - 726
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    The dynamic behavior of the R-ALOHA packet broadcast system with multipacket messages is analyzed in this paper. It is assumed that each user handles one message at a time and the number of packets in a message is geometrically distributed. A Markovian model of the system is first formulated which explicitly contains the influence of the propagation delay of the broadcast channel. An approximate technique called equilibrium point analysis (EPA) is utilized to analyze the multidimensional Markov chain. The system stability behavior and the throughput-average message delay performance are demonstrated by the EPA. Numerical results from both analysis and simulation are given to assess the accuracy of the analytic results. Applying the analytic results to the slotted ALOHA with single packet messages, we prove mathematically that a method by Kleinrock and Lam for taking into account the influence of the propagation delay is an excellent approximation. View full abstract»

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  • A Parity Structure for Large Remotely Located Replicated Data Files

    Page(s): 727 - 730
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    This paper proposes a parity structure for large remotely located replicated data files. The parity structure can accomplish the following objectives. 1) Ascertain with a high degree of confidence whether two or more files are identical, using a very small amount of communication. 2) If there is disagreement between two files, the disagreeing portion can be located simply and with a small amount of communication. 3) Memory faults within each individual file can be detected simply and with high probability. View full abstract»

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  • Dynamic Time Warp Pattern Matching Using an Integrated Multiprocessing Array

    Page(s): 731 - 744
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    Dynamic time warping is a well-established technique for time alignment and comparison of speech and image patterns. This paper decribes the architecture, algorithms, and design of a CMOS integrated processing array used for computing the dynamic time warp algorithm. Emphasis is placed on speech recognition applications because of the real-time constraints imposed by isolated and continuous speech recognition. View full abstract»

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  • A Two's Complement Array Multiplier Using True Values of the Operands

    Page(s): 745 - 747
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    A new algorithm for implementing the two's complement multiplication of an m × n bit number is described. By interpreting certain positive partial product bits as negative, a parallel array is developed which has the advantage of using only one type of adder cell. A comparison with the Pezaris and Baugh-Wooley arrays is presented, showing that the new array is as fast as the Pezaris array and uses less hardware than the Baugh-Wooley implementation. View full abstract»

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  • Solution of an Open Problem on Probabilistic Grammars

    Page(s): 748 - 750
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    It has been proved that when the production probabilities of an unambiguous context-free grammar G are estimated by the relative frequencies of the corresponding productions in a sample S from the language L(G) generated by G, the expected derivation length and the expected word length of the words in L(G) are precisely equal to the mean derivation length and the mean world length of the words in the same S, respectively. View full abstract»

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  • Two VLSI Structures for the Discrete Fourier Transform

    Page(s): 750 - 754
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    Two VLSI structures for the computation of the discrete Fourier transform are presented. The first structure is a pipeline working concurrently on different transforms. It is shown that it matches, within a constant factor, the theoretical lower bounds for area versus data rate. The second structure is a simple modification of the first one; it works on a single transform at a time, and it matches within a constant factor the theoretical area-time lower bounds. View full abstract»

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  • A Simplified Method to Calculate Failure Times in Fault-Tolerant Systems

    Page(s): 754 - 756
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    A simplified method is presented to calculate moments of failure time and residual lifetime of a fault-tolerant system. The method is based on recent results in queueing theory. Its effectiveness is illustrated by considering a dual repairable system from the literature. View full abstract»

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  • A VLSI Network for Variable Size FFT's

    Page(s): 756 - 760
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    A network for the evaluation of the fast Fourier transform (FFT) is presented. Such a network is able to compute, in parallel, the FFT's of arbitrary partitions in powers of two of the N input elements. It is shown that, under a VLSI model of computations, such a design requires the same asymptotical area and attains the same throughput as the corresponding network for the evaluation of a single N-element FFT. View full abstract»

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  • Analysis of a Local-Area Bus System with Controlled Access

    Page(s): 760 - 763
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    The performance analysis of a local-area bus access scheme is presented, which is characterized by an alternating sequence of scheduling and data-transmission intervals. For different scheduling disciplines, viz., fixed and variable priorities, and "shortest-packet-first," we derive explicit results for the mean packet-transfer delay. Our results give insight into the question of fairness among the stations, and the potential for performance improvement by sophisticated scheduling. View full abstract»

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  • Reservation Channel Access Protocol for High Speed Local Networks with Star Configurations

    Page(s): 763 - 766
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    In a wideband communication channel (> 100 MHz) local network, the propagation delay becomes comparable to the packet transmission time. As a result, CSMA-type protocols may not provide efficient channel utilization. A new channel access protocol, contention based channel reservation (CBCR) that is based on channel reservation is proposed in this paper. Our investigation reveals that the new channel access protocol yields better performance than that of CSMA-type protocols for operating in these high data rate environments. Thus, channel reservation allocation is a good alternative to the contention strategy for high speed local networks. View full abstract»

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  • On the Load Balancing Bus Accessing Scheme

    Page(s): 766 - 770
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    We describe a new technique for accessing a shared bus in a distributed computing environment. The load balancing bus accessing scheme can be modeled by a new station type that can be incorporated in a BCMP multiple class queueing network model of the distributed system. We show one simple means of implementing the load balancing scheme. View full abstract»

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  • A Symbolic Simulator for Microprogram Development

    Page(s): 770 - 774
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    Symbolic execution can be a powerful aid for microprogram development. This note describes a symbolic microprograni simulator which is used in developing microprograms for a signal processor and gives a brief example of its use. Implementation issues and cost effectiveness of this approach are also discussed. View full abstract»

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  • A Statistical Study of the Performance of a Task Scheduling Algorithm

    Page(s): 774 - 777
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    In this note we report the results of an experimental investigation on the performance of the very simple level scheduling algorithm for unit time task systems. Although the problem of the construction of optimal k-processor schedules for unit time tasks is NP-complete, the experimental study suggests that this efficient linear time algorithm can produce optimal schedules most of the time in the sense that the probability of producing an optimal schedule using this efficient linear time algorithm is at least 0.9 for over 700 cases randomly constructed in our experiment. View full abstract»

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  • Greedy Diagnosis of Hybrid Fault Situations

    Page(s): 777 - 782
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    For hybrid fault situations (that is, bounded combinations of permanent and intermittent faults) in a classical PMC diagnosable system [1], the identification of faulty units has heretofore required that testing be patiently and perhaps unrealistically repeated until the test results obtained are consistent with permanent fault situations. As a consequence, intermediate test results go unused. Moreover, the occurrence of test results consistent with permanent fault situations will, in generaL, be a rare event. View full abstract»

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  • A Design for Directed Graphs with Minimum Diameter

    Page(s): 782 - 784
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    This paper proposes a simple procedure for the design of small-diameter graphs. It can be used to construct a directed graph whose diameter is less than or equal to that of any previously proposed graph. View full abstract»

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  • IEEE Computer Society Publications

    Page(s): 784
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    Freely Available from IEEE
  • Compsac83

    Page(s): 784
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    Freely Available from IEEE

Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Albert Y. Zomaya
School of Information Technologies
Building J12
The University of Sydney
Sydney, NSW 2006, Australia
http://www.cs.usyd.edu.au/~zomaya
albert.zomaya@sydney.edu.au