IEEE Transactions on Computers

Issue 7 • July 1983

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  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1983, Page(s): c1
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  • IEEE Computer Society

    Publication Year: 1983, Page(s): c2
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  • Editor's Notice

    Publication Year: 1983, Page(s):601 - 602
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  • Equivalence of the Arbiter, the Synchronizer, the Latch, and the Inertial Delay

    Publication Year: 1983, Page(s):603 - 614
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (3434 KB)

    An axiomatic method for proving correctness properties about digital circuit implementations under the influence of asynchronous inputs is presented. This method, termed hardware correctness, is used to prove properties about a target digital circuit that is implemented in terms of constituent digital circuits. The proof consists of deducing theorems about properties of the target circuit from kno... View full abstract»

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  • Error-Correcting Codes with Byte Error-Detection Capability

    Publication Year: 1983, Page(s):615 - 621
    Cited by:  Papers (32)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (2244 KB)

    Single error-correcting and double error-detecting codes capable of detecting all single byte errors are important for practical applications. They can be used to enhance the reliability and the data integrity of computer memory systems. Here we present the construction of these codes. The construction techniques are developed from the theory of orthogonal flats in finite Euclidean geometry. View full abstract»

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  • An Abstract Model of Behavior for Hardware Descriptions

    Publication Year: 1983, Page(s):621 - 637
    Cited by:  Papers (33)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (5919 KB)

    As part of our research on the Carnegie-Mellon University Design Automation System, we have been investigating methods for proving that the system produces correct designs from correct specifications. We have developed a mathematical model for the behavior of hardware descriptions, which we have used to prove that some of the optimizing transformations used in the design system preserve behavioral... View full abstract»

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  • Graph Theoretical Analysis and Design of Multistage Interconnection Networks

    Publication Year: 1983, Page(s):637 - 648
    Cited by:  Papers (136)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (3466 KB)

    This paper introduces two graph theoretic models that provide a uniform procedure for analyzing 2n-input/2n-output Multistage Interconnection Networks (MIN's), implemented with 2-input/2-output Switching Elements (SE's) and satisfying a characteristics called the "buddy property." These models show that all such n-stage MIN's are topologically equivalent and hence prove that one MIN can be impleme... View full abstract»

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  • Expected Capacity of (m2)-Networks

    Publication Year: 1983, Page(s):649 - 657
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (2694 KB)

    A concentrator is an interconnection network with n inputs and m outputs, n > m, wherein any specified subset of inputs of size less than or equal to some number, called the network's actual capacity, can always be simultaneously connected to some equal-sized but unspecifiable subset of outputs. Guaranteed throughput as described by actual capacity has heretofore been the principle measure for ... View full abstract»

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  • Torus and Other Networks as Communication Networks With Up to Some Hundred Points

    Publication Year: 1983, Page(s):657 - 666
    Cited by:  Papers (15)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (4181 KB)

    To be used as message passing networks of computers we consider graphs of degree D and diameter K. To obtain bounds for the average distance Ak (and K) with any given number N of nodes and given D we generalize Moore graphs to Moore* graphs minimizing Ak. View full abstract»

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  • Binary Search in a Multiprocessing Environment

    Publication Year: 1983, Page(s):667 - 677
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (2783 KB)

    In this paper we consider variations on the binary search algorithm when placed in the context of a multiprocessing environment. Several organizations are investigated covering the spectrum from total independence (or free competition for access to common resources) to cooperation as in SIMD architectures. It is assumed that the two main sources of overhead are memory interference and interprocess... View full abstract»

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  • The Analysis and Design of Some New Sorting Machines

    Publication Year: 1983, Page(s):677 - 683
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (3902 KB)

    A classification method for parallel sorting architectures is presented for comparison of existing designs. Some common drawbacks of these parallel sorters are noted: in general, they are limited by their data accessing mechanism, their hardware utilization is low, and their sorting speed is in some sense independent of the number of sorting elements used in the architecture. In this paper we pres... View full abstract»

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  • Area—Time Optimal VLSI Circuits for Convolution

    Publication Year: 1983, Page(s):684 - 688
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (2224 KB)

    A family of VLSI circuits is presented to perform open convolution, i.e., polynomial multiplication. The circuits are all based on a recursive construction and are therefore particularly well adapted to automated design. All the circuits presented are optimal with respect to the area–time2 tradeoff, and, depending on the degree of paralleism or pipeline, they range from a compact but slow co... View full abstract»

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  • Performance of Cross-Bar Multiprocessor Systems

    Publication Year: 1983, Page(s):689 - 695
    Cited by:  Papers (19)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1007 KB)

    This paper presents some mathematical and simulation models for evaluating the performance of cross-bar multiprocessor systems, as well as an evaluation of system's cost/performance ratio. View full abstract»

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  • A Self-Test Hardwired Control Section

    Publication Year: 1983, Page(s):695 - 696
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (388 KB)

    A fault detect mechanism is described for hardwired control logic. The mechanism takes advantage of inherent redundancy in the control logic design style which assigns a unique flip-flop to each machine state. The mechanism is capable of detecting all single stuck-at faults, as well as many multiple faults and intermittents within the control section. View full abstract»

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  • IEEE Computer Society Publications

    Publication Year: 1983, Page(s): 696
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  • Information for authors

    Publication Year: 1983, Page(s): 696
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org