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Computers, IEEE Transactions on

Issue 3 • Date March 1983

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Displaying Results 1 - 19 of 19
  • IEEE Transactions on Computers - Table of contents

    Page(s): c1
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    Freely Available from IEEE
  • IEEE Computer Society

    Page(s): c2
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    Freely Available from IEEE
  • Single Row Routing

    Page(s): 209 - 220
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    The automated design of multilayer printed circuit boards is of great importance in the physical design of complex electronic systems. Wire routing is a crucial step in the design process. In this paper, the single row routing problem is considered. First, we discuss the relevance of single row routing in the context of the general routing problem. Then, we show that relaxing the restriction that backward moves are not allowed can result in smaller street congestions when there are at least four tracks in each street. Next, we obtain an O((2k)!kn log k) algorithm to determine whether or not an instance involving n nodes can be laid out (without backward moves) when only k tracks per street are available. With the additional restriction that wires are not permitted to cross streets, an efficient (O(n2)) algorithm is obtained. This restricted problem is shown to be related to a furnace assignment problem. View full abstract»

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  • The Isomorphism of Simple File Allocation

    Page(s): 221 - 232
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    In this paper, we show that the simple file allocation problem in computer science is isomorphic to the single commodity warehouse location problem in operations research. In simple file allocation, costs due to query and update accesses and storage are considered. Design requirements such as reliability, availability, and delay are not taken into account. Due to this isomorphism, many techniques which have been developed for the warehouse location problem can be applied to solve the simple file allocation problem. Furthermore, there are techniques and conditions developed for one problem which match closely with techniques and conditions developed for the other problem. Based on a combined set of conditions developed in computer science and operations research, a heuristic for file allocation is presented. View full abstract»

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  • File Allocation in a Distributed Computer Communication Network

    Page(s): 232 - 244
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    An algorithm is presented to determine locations for the storage of copies of files in store-and-forward computer communications networks. The algorithm determines storage locations which minimize the sum of network file storage costs and message transmission costs. Networks that use adaptive routing techniques are the primary focus. Feasible file locations must satisfy network performance requirements for file availability and delay by message class. An effective method of evaluating delay constraints for networks using adaptive routing techniques is introduced. The algorithm uses the solution to a p-median problem to identify initial candidate file placements. Interaction between a set of file movement rules and a network simulator is employed to modify initial placements to fmd near-optimal locations which satisfy the network performance constraints. View full abstract»

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  • A Quantization Approximation for Modeling Computer Network Nodal Queueing Delay

    Page(s): 245 - 253
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    A new approximation model for the analysis of a finite buffer GI/G/1 system is presented. The approach consists of formulating the computer node mean waiting time from a discrete time marginal overflow customer per time slot solution of a continuous marginal overflow time per customer solution. The key to the model solution is the quantization of the distribution (fu(u)) of the difference between customer service time and customer interarrival time to obtain areas of sections (quantiles) of this probability density function. These quantiles represent the entries of the probability transition matrix of the change in the number of customers allowed in the queue. Irreducible Markov chains represent these uniform quantization lower and upper bound steady state buffer occupancy solutions for the number of customers in the queue at time slot j. A guideline for selecting the optimal quantization interval width is the numerical relation observed between the optimal range of Peak Measurement Accuracy and Peak Measurement Complexity for finite areas of fu(u). View full abstract»

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  • An Efficient Implementation of Batcher's Odd-Even Merge Algorithm and Its Application in Parallel Sorting Schemes

    Page(s): 254 - 264
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    An algorithm is presented to merge two subfiles of size n/2 each, stored in the left and the right halves of a linearly connected processor array, in 3n/2 route steps and log n compare-exchange steps. This algorithm is extended to merge two horizontally adjacent subfiles of size m × n/2 each, stored in an m × n mesh-connected processor array in row-major order, in m + 2n route steps and log mn compare-exchange steps. These algorithms are faster than their counterparts proposed so far. View full abstract»

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  • An Efficient Parallel Algorithm for the Solution of Large Sparse Linear Matrix Equations

    Page(s): 265 - 273
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    An algorithm for the parallel solution of large sparse sets of linear equations, given their factor matrices, is developed. It is aimed at efficient practical implementation on a processor of the multiple instruction multiple data stream (MIMD) type. The software required to implement the algorithm is described. In addition, the amount of memory necessary for data retention during execution is considered and related to that which is required on single processor systems. Hardware developed for the implementation of the algorithm is described. Bus contention for the system is outlined and shown to be insignificant. Possible bus contention problems for systems differing in the number of processors and speed of processing elements are also considered. A simulator modeling the execution of the algorithm on large systems has been implemented. The performance of the algorithm, in terms of execution speed enhancement relative to the theoretical maximum, is shown to be good. View full abstract»

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  • A New Design Method for m-Out-of-n TSC Checkers

    Page(s): 273 - 283
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    The paper presents a new method for designing efficient TSC checkers for m-out-of n codes. The method is based on the partitioning of the input code variables into an arbitrary number of r classes. The paper establishes the necessary design conditions that must hold among m, n and r. The checker is basically composed of an m/n to l/z subchecker concatenated with an l/z to 1/2 subchecker. A cost analysis performed reveals that the most economical checkers are obtained for values of r equal to 3, or 4 for the majority of m/n codes with n ≤ 4m. Comparison with earlier designs reveals impressive improvement both in logic complexity and testing complexity. View full abstract»

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  • Asynchronous and Clocked Control Structures for VSLI Based Interconnection Networks

    Page(s): 284 - 293
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    A central issue in the design of multiprocessor systems is the interconnection network which provides communication paths between the processors. For large systems, high bandwidth interconnection networks will require numerous "network chips" with each chip implementing some subnetwork of the original larger network. Modularity and growth are important properties for such networks since multiprocessor systems may vary in size. This paper is concerned with the question of timing control of such networks. Two approaches, asynchronous and clocked, are used in the design of a basic network switching module. The modules and the approaches are then modeled and equations for network time delay are developed. These equations form the basis for a comparison between the two approaches. The importance of clock distribution strategies and clock skew is quantified, and a network clock distribution scheme which guarantees equal length clock paths is presented. View full abstract»

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  • A Combinatorial Limit to the Computing Power of VLSI Circuits

    Page(s): 294 - 300
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    We introduce a property of Boolean functions, called transitivity which consists of integer, polynomial, and matrix products as well as of many interesting related computational problems. We show that the area of any circuit computing a transitive function grows quadratically with the circuit's maximum data rate, expressed in bits/S. This result provides a precise analytic expression of an area-time tradeoff for a wide class of VLSI circuits. Furthermore (as shown elsewhere), this tradeoff is achievable. We have thus matching (to within a constant multiplicative factor) upper and lower complexity bounds for the three above products, in the VLSI circuits computational model. View full abstract»

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  • A Parallel-Pipeline Architecture of the Fast Polynomial Transform for Computing a Two-Dimensional Cyclic Convolution

    Page(s): 301 - 306
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    In this paper, a parallel-pipeline, radix-2 architecture is proposed to implement the fast polynomial transform (FPT). It is shown that such a structure can be used to efficiently compute a two-dimensional convolution of d1× d2complex number points, where d1 = 2m-r+1and d2= 2mfor 1 ≤ r ≤ m. View full abstract»

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  • Binary Trees and Parallel Scheduling Algorithms

    Page(s): 307 - 315
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    This paper examines the use of binary trees in the design of efficient parallel algorithms. Using binary trees, we develop efficient algorithms for several scheduling problems. The shared memory model for parallel computation is used. Our success in using binary trees for parallel computations, indicates that the binary tree is an important and useful design tool for parallel algorithms. View full abstract»

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  • A Tree Representation of Combinational Networks

    Page(s): 315 - 319
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    A tree representation of a combinational network is developed. An algorithm is proposed for finding the functional expression realized by the network. The tree representation has storage requirement linear with respect to the number of input-output paths in the network. It is shown that rmding the complementary function and generating network SPOOF can be performed efficiently on the tree structure. View full abstract»

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  • On a Novel Approach of Fault Detection in an Easily Testable Sequential Machine with Extra Inputs and Extra Outputs

    Page(s): 323 - 325
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    By augmenting a given sequential machine M with two extra input symbols Ie1 and Ie2 and with one extra output terminal Z', a method is developed in this paper for designing an efficient checking experiment for the machine M and for its fault diagnosis to cover the types of faults which may result in an increase in the number of states of the original machine M. The method is an extension of the works of Fujiwara et al.[6], and the scheme of modification never alters the modified machine M' from its easily testable nature as defined by Fujiwara et al [16]. The checking sequences exhibit remarkable savings of the number of input symbols for many sequential machines having a large number of states as compared to that of Fujiwara et al [16]. View full abstract»

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  • Error-Correcting Codes in Binary-Coded Radix-r Arithmetic

    Page(s): 326 - 328
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    This paper presents a new class of AN codes of high efficiency capable of correcting single errors in radix-r arithmetic with the binary coded digits—BCr—system. The errors corrected within a single radix-r digit are single errors of the binary digits with weight ±wi≤ r–1,i=1,2,···, m, which are used to encode the BCr digits. The corresponding arithmetic unit is made out of slices, one for each BCr digit. The AN codes considered have a generator A of the form A = τ·p where τ, p odd and rp=n-1 ≤ τ < p. The paper establishes the selection criteria of r and p such that the code range of the AN codes is equal to M = rk± 1. The criteria are applied to the BCD system, and we determine all τ < 100 and p < 200 for the most important BCD codes with weights ± wi < r –1, i = 1, 2, 3, 4. For each BCD code, the paper gives the numbers τ < 100 for which AN codes exist, and the maximum code efficiency E = 2·m·k/(A-1) attained at some p < 200. View full abstract»

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  • IEEE Computer Society Publications

    Page(s): 328
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    Freely Available from IEEE
  • Call for Papers

    Page(s): 328
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    Freely Available from IEEE

Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Albert Y. Zomaya
School of Information Technologies
Building J12
The University of Sydney
Sydney, NSW 2006, Australia
http://www.cs.usyd.edu.au/~zomaya
albert.zomaya@sydney.edu.au