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IEEE Transactions on Computers

Issue 12 • Dec. 1983

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Displaying Results 1 - 25 of 28
  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1983, Page(s): c1
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    Freely Available from IEEE
  • IEEE Computer Society

    Publication Year: 1983, Page(s): c2
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    Freely Available from IEEE
  • An Inductive Assertion Method for Register Transfer Level Design Verification

    Publication Year: 1983, Page(s):1073 - 1080
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3054 KB)

    This paper extends Floyd's inductive assertion method to formal verification of register transfer level (RTL) hardware descriptions. An RTL description with imbedded assertions about machine state will be the input to the verifier. The formal semantics of an RTL language for synchronous designs are defined, to make mechanical generation of verification conditions (VC's) possible. These VC's are to... View full abstract»

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  • Design and Performance of Generalized Interconnection Networks

    Publication Year: 1983, Page(s):1081 - 1090
    Cited by:  Papers (76)  |  Patents (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2870 KB)

    This paper introduces a general class of self-routing interconnection networks for tightly coupled multiprocessor systems. The proposed network, named a "generalized shuffle network (GSN)," is based on a new interconnection pattern called a generalized shuffle and is capable of connecting any number of processors M to any number of memory modules N. The technique results in a variety of interconne... View full abstract»

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  • The Performance of Multistage Interconnection Networks for Multiprocessors

    Publication Year: 1983, Page(s):1091 - 1098
    Cited by:  Papers (340)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2506 KB)

    This paper studies the performance of unbuffered and buffered, packet-switching, multistage interconnection networks. We begin by reviewing the definition of banyan networks and introducing some generalizations of them. We then present an asymptotic analysis of the performance of unbuffered banyan networks, thereby solving a problem left open by Patel. We analyze the performance of the unbuffered ... View full abstract»

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  • A Class of Redundant Path Multistage Interconnection Networks

    Publication Year: 1983, Page(s):1099 - 1108
    Cited by:  Papers (68)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2903 KB)

    A general class of fault-tolerant multistage interconnection networks is presented, wherein fault-tolerance is achieved by providing multiple disjoint paths between every input and output. These networks are derived from the Omega networks and as such retain all the connection properties of the parent networks in the absence of faults. An R-path network in this class can tolerate (R-1) arbitrary f... View full abstract»

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  • Optimal Parallel Scheduling of Gaussian Elimination DAG's

    Publication Year: 1983, Page(s):1109 - 1117
    Cited by:  Papers (19)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2996 KB)

    A parallel algorithm for Gaussian elimination (GE) is described, which solves a linear system of size n using m ≤ n parallel processors and a shared random access memory. Converting the serial GE algorithm to parallel form involves scheduling its computation DAG (directed acyclic graph) on m processors. A lower bound for schedule length is established for dense GE DAG's and it is proved that... View full abstract»

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  • Ultrahigh Reliability Prediction for Fault-Tolerant Computer Systems

    Publication Year: 1983, Page(s):1118 - 1127
    Cited by:  Papers (58)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3055 KB)

    A review and a critical evaluation of a representative class of state-of-the-art models for ultrahigh reliability prediction is presented. This evaluation naturally leads us to a new model for ultrahigh reliability prediction now under development. The new model combines the flexibility and accuracy of simulation with the speed of analytic models. View full abstract»

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  • A Pipelined Distributed Arithmetic PFFT Processor

    Publication Year: 1983, Page(s):1128 - 1136
    Cited by:  Papers (7)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2914 KB)

    Previous experience in implementing the prime factor Fourier transform (PFFT) showed that it was much more difficult to do than the FF because of its complicated structure. In most FFT implementations the "butterfly" structure is the basic arithmetic element implemented. It is much simpler than the equivalent PFFT unit. View full abstract»

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  • On the Acceleration of Test Generation Algorithms

    Publication Year: 1983, Page(s):1137 - 1144
    Cited by:  Papers (485)  |  Patents (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2515 KB)

    In order to accelerate an algorithm for test generation, it is necessary to reduce the number of backtracks in the algorithm and to shorten the process time between backtracks. In this paper, we consider several techniques to accelerate test generation and present a new test generation algorithm called FAN (fan-out-oriented test generation algorithm). It is shown that the FAN algorithm is faster a... View full abstract»

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  • Exhaustive Test Pattern Generation with Constant Weight Vectors

    Publication Year: 1983, Page(s):1145 - 1150
    Cited by:  Papers (50)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2159 KB)

    We develop in this paper a simple way of generating a test set which simultaneously provides exhaustive pattern testing with respect to all input subsets of a logic circuit up to a certain size. It is shown that such a test set may be formed with vectors of a particular set of weights. Main theorems and examples are established and illustrated in the binary case (for 2-value logic circuits) and th... View full abstract»

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  • Two-Level Replacement Decisions in Paging Stores

    Publication Year: 1983, Page(s):1151 - 1159
    Cited by:  Papers (11)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2984 KB)

    One of the primary motivations for implementing virtual memory is its ability to automatically manage a hierarchy of storage systems with different characteristics. The composite system behaves as if it were a single-level system having the more desirable characteristics of each of its constituent levels. In this paper we extend the virtual memory concept to within the top level of a two-level hie... View full abstract»

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  • VLSI Array Design Under Constraint of Limited I/O Bandwidth

    Publication Year: 1983, Page(s):1160 - 1170
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2943 KB)

    VLSI computing arrays for matrix multiplication and covariance matrix inversion have applications in many fields. Under the constraint of limited I/O bandwidth of the host system or the computing array, three configurations for the interfacing and controlling of a multiplication array to achieve optimal performance under different adverse situations are examined. The three configurations are multi... View full abstract»

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  • The VLSI Complexity of Sorting

    Publication Year: 1983, Page(s):1171 - 1184
    Cited by:  Papers (134)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3238 KB)

    The area-time complexity of sorting is analyzed under an updated model of VLSI computation. The new model makes a distinction between "processing" circuits and "memory" circuits; the latter are less important since they are denser and consume less power. Other adjustments to the model make it possible to compare pipelined and nonpipelined designs. View full abstract»

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  • Transposition of Matrix Stored on Sequential File

    Publication Year: 1983, Page(s):1185 - 1188
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (754 KB)

    A family of algorithms is presented for transposition of a matrix which is stored sequentially on a file. The basic method is a variant of the balanced tape merge algorithm. The new balanced merge transposition method is compared to published methods. View full abstract»

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  • Security Information Flow in Multidimensional Arrays

    Publication Year: 1983, Page(s):1188 - 1191
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (700 KB)

    The problem of security flow into n-dimensional arrays is considered. It is shown that in the security flow analysis for an array assignment A(B1, B2···,Bn) = 〈expression〉, it is sufficient to analyze the flows Bj→ A( B1, B2,··· Bn), i.e., show that L[Bj]≤ L[A(B1<... View full abstract»

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  • A Preliminary Evaluation of Trace Scheduling for Global Microcode Compaction

    Publication Year: 1983, Page(s):1191 - 1194
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (933 KB)

    Fisher has recently described a new procedure for global microcode compaction which he calls "trace scheduling." We have implemented this procedure and tested it on several microcode sequences. We report in this correspondence on the relative effectiveness of local compaction, manual compaction, and trace scheduling on these sequences. View full abstract»

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  • Universal Tests for Detection of Input/Output Stuck-At and Bridging Faults

    Publication Year: 1983, Page(s):1194 - 1198
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1014 KB)

    In this correspondence we present universal tests for detection of single and multiple stuck-at and bridging faults in combinational and sequential networks. View full abstract»

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  • Good Controllability and Observability Do Not Guarantee Good Testability

    Publication Year: 1983, Page(s):1198 - 1200
    Cited by:  Papers (25)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (536 KB)

    In this paper we show that good controllability and observability do not guarantee good testability. In fact, one can easily find examples of faults that are difficult or impossible to detect, although both the controllability and observability figures are good. View full abstract»

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  • Comments on "Optimal Design of Distributed Information Systems"

    Publication Year: 1983, Page(s):1200 - 1201
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (392 KB)

    Deficiencies in the formulation of the model for optimal design of the distributed network are pointed out. These concern the existence of communication links and routing variables for updates. Several feasible solutions, with a lower cost than the one given in the above paper for the example discussed, are presented. These establish the inadequacy of the procedure adopted to arrive at the optimal... View full abstract»

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  • Optimizing Contiguous-Element Region Selection for Virtual Memory Systems

    Publication Year: 1983, Page(s):1201 - 1203
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (651 KB)

    Contiguous element region selection is a fundamental step in many image analysis applications. This application is often run on computers with virtual memory systems. The page fault behavior of the contiguous element selection algorithm is greatly influenced by the ordering of the nearest neighbor search pattern. The execution time of the algorithm can be cut in half for important instances of rea... View full abstract»

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  • Optimal Algorithms for the Intersection and the Minimum Distance Problems Between Planar Polygons

    Publication Year: 1983, Page(s):1203 - 1207
    Cited by:  Papers (34)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1095 KB)

    Two planar geometric problems relating to a convex n-gon P and a simple nonconvex m-gon Q are considered. View full abstract»

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  • Measured Flip-Flop Responses to Marginal Triggering

    Publication Year: 1983, Page(s):1207 - 1209
    Cited by:  Papers (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (679 KB)

    Test data are presented characterizing the marginal triggering response of several types of flip-flops. This characterization, which is seldom measured or specified, is required to predict the reliability of synchronizer designs. View full abstract»

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  • A Faster 8-Bit Carry Circuit

    Publication Year: 1983, Page(s):1209 - 1211
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (643 KB)

    A modification of the Chen-Kuck 8-bit carry circuit is presented with one less gate delay and a proof is given that this is the best possible time. The corresponding results for longer length circuits are summarized. View full abstract»

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  • Symmetric and Threshold Boolean Functions Are Exhaustive

    Publication Year: 1983, Page(s):1211 - 1212
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (446 KB)

    The worst-case number of variable evaluations (testing cost) of Boolean functions is examined. Following up on a result by Rivest and Vuillemin, we show that all symmetric as well as all linearly separable Boolean functions are exhaustive, that is, have a pessimal worst-case testing cost. View full abstract»

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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org