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IEEE Transactions on Computers

Issue 11 • Nov. 1983

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Displaying Results 1 - 18 of 18
  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1983, Page(s): c1
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    Freely Available from IEEE
  • IEEE Computer Society

    Publication Year: 1983, Page(s): c2
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  • Strategies for Managing the Register File in RISC

    Publication Year: 1983, Page(s):977 - 989
    Cited by:  Papers (21)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4800 KB)

    The RISC (reduced instruction set computer) architecture attempts to achieve high performance without resorting to complex instructions and irregular pipelining schemes. One of the novel features of this architecture is a large register file which is used to minimize the overhead involved in procedure calls and returns. This paper investigates several strategies for managing this register file. Th... View full abstract»

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  • Processor Architectures for Two-Dimensional Convolvers Using a Single Multiplexed Computational Element with Finite Field Arithmetic

    Publication Year: 1983, Page(s):989 - 1001
    Cited by:  Papers (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (7063 KB)

    This paper describes the theory, simulation, and construction of a two-dimensional number theoretic transform (NTT) convolver. The convolver performs indirect convolution by using the cyclic convolution property of a class of generalized discrete Fourier transforms (DFT's) defined over rings isomorphic to direct sums of Galois fields. The paper first presents the theoretical development of the com... View full abstract»

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  • Cooperating Reduction Machines

    Publication Year: 1983, Page(s):1002 - 1012
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3559 KB)

    This paper presents a concept and a system architecture for the concurrent execution of program expressions of a concrete reduction language based on λ-expressions. View full abstract»

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  • A Residue Number System Implementation of the LMS Algorithm Using Optical Waveguide Circuits

    Publication Year: 1983, Page(s):1013 - 1028
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4054 KB)

    A detailed design of a real-time data processor based on the residue number system is presented which uses near-term optical waveguide devices and concepts. The optical computational units consist of cascaded, mask-programmable arrays of total internal reflection electrooptic switches arranged on a LiNbO3 substrate in a serpentine configuration. This paper describes these computational units and t... View full abstract»

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  • Delayed-Staging Hierarchy Optimization

    Publication Year: 1983, Page(s):1029 - 1037
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2655 KB)

    A geometric programming model is developed to optimize delayed-staging (DS) storage hierarchies. These hierarchies have direct paths between the CPU and the k fastest storage levels (k = 1 in a linear hierarchy), allowing for some concurrency in the flow of data through the hierarchy. The criterion for optimization is the minimization of average hierarchy access time subject to budgetary limitatio... View full abstract»

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  • An Easily Testable Design of Programmable Logic Arrays for Multiple Faults

    Publication Year: 1983, Page(s):1038 - 1046
    Cited by:  Papers (40)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2296 KB)

    In this paper, the problem of fault detection for multiple faults in programmable logic arrays (PLA's) is discussed. An easily testable design of PLA's has been proposed which has the following properties: 1) for a PLA with n inputs, m product terms, there exists a test set such that the test patterns do not depend on the function realized by the PLA; 2) the number of tests to detect multiple stuc... View full abstract»

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  • Fourier Transforms in VLSI

    Publication Year: 1983, Page(s):1047 - 1057
    Cited by:  Papers (115)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3551 KB)

    This paper surveys nine designs for VLSI circuits that compute N-element Fourier transforms. The largest of the designs requires O(N2 log N) units of silicon area; it can start a new Fourier transform every O(log N) time units. The smallest designs have about 1/Nth of this throughput, but they require only 1/Nth as much area. View full abstract»

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  • Spectral Fault Signatures for Internally Unate Combinational Networks

    Publication Year: 1983, Page(s):1058 - 1062
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1007 KB)

    A method is described for the derivation of fault signatures for certain classes or irredundant combinational networks. These signatures consist of a set of values derived from the network. Any stuck-at fault causes at least one of the values to change. The signatures provide complete fault detection for all single stuck-at faults. They are usually short and never contain more than n + 1 values fo... View full abstract»

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  • A Simple Derivation of the MVA and LBANC Algorithms from the Convolution Algorithm

    Publication Year: 1983, Page(s):1062 - 1064
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (587 KB)

    The convolution algorithm, the mean value analysis (MVA) algorithm, and the LBANC algorithm are major algorithms for the solution of closed product-form queueing networks. For fixed-rate service centers, the efficiency of each algorithm is greatly improved by a recursive solution. We show that the recursive relations in all three algorithms are closely related so that each one can be easily derive... View full abstract»

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  • Efficient Iterated Rotation of an Object

    Publication Year: 1983, Page(s):1064 - 1067
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (857 KB)

    This paper presents a more efficient method for iterated rotation in three dimensions where multiple points are being rotated by multiple angles about the same axis, as would he done in robotic simulation or computer graphic animation. General axes that do not necessarily pass through the origin and multiple composed rotations are also handled. The algorithm is numerically well conditioned for all... View full abstract»

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  • A Variable-Length Shift-Register

    Publication Year: 1983, Page(s):1067 - 1069
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (556 KB)

    A new way of implementing the variable-length shift-register function is presented. It utilizes two bidirectional shift registers of length N/2 where N is the maximum length anticipated for any input string. View full abstract»

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  • A Structural Redundancy in d-Sequences

    Publication Year: 1983, Page(s):1069 - 1070
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (331 KB)

    This note reports the observation that the reciprocals of primes have an excess of zeros. For a binary representation only 2 percent of the cases appear to have more ones than zeros. View full abstract»

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  • An Efficient Approach for Fault Diagnosis in a Boolean n-Cube Array of Microprocessors

    Publication Year: 1983, Page(s):1070 - 1071
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (393 KB)

    In this correspondence a O(n3)-time algorithm for fault diagnosis in an n-cube connected array of processors is presented using the notion of candidate processors and syndrome information digraphs. View full abstract»

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  • Comments on "The Prime Memory Systems for Array Access"

    Publication Year: 1983, Page(s): 1072
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (105 KB)

    A simple technique for performing mod (or modulus) M operations, where M is a prime number, is described. This technique can be applied to the prime memory system as described by Lawrie and Vora [1]. View full abstract»

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  • IEEE Computer Society Publications

    Publication Year: 1983, Page(s): 1072
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    Freely Available from IEEE
  • Information for authors

    Publication Year: 1983, Page(s): 1072
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org