IEEE Transactions on Computers

Issue 10 • Oct. 1983

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  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1983, Page(s): c1
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    Freely Available from IEEE
  • IEEE Computer Society

    Publication Year: 1983, Page(s): c2
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  • Merit's Evolution—Statistically Speaking

    Publication Year: 1983, Page(s):881 - 902
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3936 KB)

    Merit links four Michigan universities with a packet-switching computer network. This network provides several interactive and batch services to the students, faculty, and researchers of these schools. While the network and its services are reviewed, this paper focuses on the statistical performance of Merit during its first ten operational years. Numerous graphs and tables present data including ... View full abstract»

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  • The Diogenes Approach to Testable Fault-Tolerant Arrays of Processors

    Publication Year: 1983, Page(s):902 - 910
    Cited by:  Papers (180)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4104 KB)

    This paper describes by a series of examples a strategy for designing testable fault-tolerant arrays of processors. The strategy achieves fault tolerance by introducing redundancy in an array's communication links rather than in its processing elements (PE's). The major characteristics of the designs produced are as follows. View full abstract»

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  • Architecture Optimization of Aerospace Computing Systems

    Publication Year: 1983, Page(s):911 - 922
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3240 KB)

    Simultaneous consideration of both performance and reliability issues is important in the choice of computer architectures for real-time aerospace applications. One of the requirements for such a fault-tolerant computer system is the characteristic of graceful degradation. A shared and replicated resources computing system represents such an architecture. In this paper, a combinatorial model is us... View full abstract»

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  • Global Compaction of Horizontal Microprograms Based on the Generalized Data Dependency Graph

    Publication Year: 1983, Page(s):922 - 933
    Cited by:  Papers (14)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (6067 KB)

    This paper describes a global compaction algorithm which can produce efficient microprograms with respect to both space and time. The algorithm depends upon a generalized data dependency graph (GDDG), which can integratedly express the concurrency of microorders and their mobility past the boundaries of basic blocks, as well as the control flow for a microprogram. In the algorithm an initial GDDG ... View full abstract»

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  • Characterizing Computers and Optimizing the FACR(l) Poisson-Solver on Parallel Unicomputers

    Publication Year: 1983, Page(s):933 - 941
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4279 KB)

    A two-parameter description of any computer is given that characterizes the performance of serial, pipelined, and array-like architectures. The first parameter (r∞) is the traditional maximum performance in megaflops, and the new second parameter (n½) measures the apparent parallelism of the computer. For computers with a single instruction stream (unicomputers), the relative performanc... View full abstract»

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  • Searching, Merging, and Sorting in Parallel Computation

    Publication Year: 1983, Page(s):942 - 946
    Cited by:  Papers (85)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2118 KB)

    We study the number of comparison steps required for searching, merging, and sorting with P processors. We present a merging algorithm that is optimal up to a constant factor when merging two lists of equal size (independent of the number of processors); as a special case, with N processors it merges two lists, each of size N, in 1.893 lg lg N + 4 comparison steps. We use the merging algorithm to ... View full abstract»

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  • Redundancy and Don't Cares in Logic Synthesis

    Publication Year: 1983, Page(s):947 - 952
    Cited by:  Papers (63)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2249 KB)

    A signal in a logical network is called redundant if it can be replaced by a constant without changing the function of the network. Detecting redundancy is important for two reasons: guaranteeing coverage in stuck-fault testing, and simplifying multilevel logic without converting to two levels. In particular, removing redundancy allows simplification in the presence of don't cares. The algorithm f... View full abstract»

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  • Greedy Diagnosis as the Basis of an Intermittent-Fault/ Transient-Upset Tolerant System Design

    Publication Year: 1983, Page(s):953 - 957
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1065 KB)

    Multiple-unit computer systems which are to be tolerant of intermittently faulty units or transiently upset units are considered in this paper. Designs for such systems, which exploit a new so-called greedy diagnosis theory, are developed. Using greedy diagnosis, assessments on the condition of a unit (intermittent-fault case) or the integrity of data (transient-upset case) can be made on the basi... View full abstract»

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  • A Class of Test Generators for Built-In Testing

    Publication Year: 1983, Page(s):957 - 959
    Cited by:  Papers (21)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (628 KB)

    Currently proposed and used schemes for built-in testing (B-I-T) use as test generators either binary counters (exhaustive testing), linear feedback shift registers (semiexhaustive testing), or ROM's containing the test vectors (prestored testing). The disadvantages of these methods have been discussed in [4], and a store-and-generate B-I-T arrangement was proposed as a compromise between the exha... View full abstract»

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  • A New Empirical Test for the Quality of Random Integer Generators

    Publication Year: 1983, Page(s):960 - 961
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (380 KB)

    In a number of applications, it is necessary to generate stimnuli: to generate random patterns when random testing of logic faults is employed, and to generate the random occurrence of events when simulation is used, to mention two. In this paper, we show a quick empirical test, which is based on a data compression method, to analyze the pseudorandom integers generated by certain types of random i... View full abstract»

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  • Direct Implementation of Discrete and Residue-Based Functions Via Optimal Encoding: A Programmable Array Logic Approach

    Publication Year: 1983, Page(s):961 - 968
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1849 KB)

    This paper presents a technique for direct truth table implementation of residue-based functions by an encoding scheme that employs programmable array logic (PAL) technology. The scheme models the basic associative memory operation, i.e., the detection of matchings between input patterns and prestored information in the PAL's. The complexity of this model is related to the amount of stored logic, ... View full abstract»

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  • Parallel Binary Adders with a Minimum Number of Connections

    Publication Year: 1983, Page(s):969 - 976
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1581 KB)

    An n-bit parallel binary adder consisting of NOR gates only in single-rail input logic is proved to require at least 17n + 1 connections for any value of n. Such an adder is proved to require at least 7n + 2 gates. An adder that attains these minimal values is shown. Also, it is concluded that some of the parallel adders with the minimum number of NOR gates derived by Lai and Muroga have the minim... View full abstract»

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  • IEEE Computer Society Publications

    Publication Year: 1983, Page(s): 976
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    Freely Available from IEEE
  • Compsac 83

    Publication Year: 1983, Page(s): 976
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    Freely Available from IEEE

Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org