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Computers, IEEE Transactions on

Issue 1 • Date Jan. 1983

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Displaying Results 1 - 16 of 16
  • IEEE Transactions on Computers - Table of contents

    Page(s): c1
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  • IEEE Computer Society

    Page(s): c2
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  • Editor's Notice

    Page(s): 1
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  • Guest Editors' Introduction Performance Evaluation of Multiple Processor Systems

    Page(s): 2 - 3
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    PERFORMANCE evaluation means to study, to analyze, and to optimize the flow of data and control information in computer systems. In doing so, the main objectives are to formally describe the real behavior of computers, to define and determine characteristic performance measures, and to develop tools for the design of optimal hardware structures and system software. View full abstract»

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  • An Integrated Instrumentation Environment for Multiprocessors

    Page(s): 4 - 14
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    This paper introduces the concept of an integrated instrumentation environment (IIE) for multiprocessors. The primary objective of such an environment is to assist the user in the process of experimentation. The emphasis in an IIE is on experiment management (including stimulus generation, monitoring, data collection and analysis), rather than on techniques for program development as in conventional programming environments. We believe the functionality of the two environments should eventually be provided in one comprehensive environment. View full abstract»

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  • Experiences with Performance Measurement and Modeling of a Processor Array

    Page(s): 15 - 31
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    The evolution of technology provides the opportunity of forming large processor ensembles working closely together. When decomposing application programs and assigning subtasks to different processors we expect not only high throughput, but also the fastest possible execution of each individual demand. The level of performance in these areas is strongly influenced by the hardware interconnection structure and by the communication software. View full abstract»

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  • The Measurement of Performance on a Highly Parallel System

    Page(s): 32 - 37
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    The problems of measuring the performance of a highly parallel multiple processor system, such as the 4096 element ICL Distributed Array Processor are presented in relation to the conventional methods used for serial processors; this is preceded by a brief description of the DAP hardware in order to. provide a framework for the discussion, together with some of the resulting implications for algorithm design. The importance of choosing algorithms for parallel computation in such a way as to make the best use of the parallelism of the hardware for the problem to be solved is discussed, and examples are given of parallel and hybrid algorithms—in the latter a mixture of serial and parallel techniques are used. A method of comparison of performance at the problem solving level is presented, which is illustrated by results obtained by DAP users studying problems which arise in a wide range of application areas. View full abstract»

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  • Shared Cache for Multiple-Stream Computer Systems

    Page(s): 38 - 47
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    Cache memory organization for parallel-pipelined multiprocessor systems is evaluated. Private caches have a cache coherence problem. A shared cache avoids this problem and can attain a higher hit ratio due to sharing of single copies of common blocks and dynamic allocation of cache space among the processes. However, a shared cache suffers performance degradation due to access conflicts. View full abstract»

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  • Effectiveness of Private Caches in Multiprocessor Systems with Parallel-Pipelined Memories

    Page(s): 48 - 59
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    A possible design alternative for improving the performance of a multiprocessor system is to insert a private cache between each processor and the shared memory. The caches act as high-speed buffers by reducing the effective memory access time, and affect the delays caused by memory conflicts. In this paper, we study the effectiveness of caches in a multiprocessor system. The shared memory is pipelined and interleaved to improve the block transfer rate, and it assumes a two-dimensional organization, previously studied under random and word access. An approximate model is developed to estimate the processor utilization and the speed-up improvement provided by the caches. View full abstract»

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  • Modeling Bus Contention and Memory Interference in a Multiprocessor System

    Page(s): 60 - 72
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    Stochastic models of contention for shared resources in an experimental multiprocessor prototype are presented and are validated with simulation and measurement results. Three modeling techniques are used (stochastic Petri nets, Markov chains, and queueing networks) that represent the system operations as Markovian stochastic processes. Each technique is best suited to a specific stage of the analysis. An integrated use of these techniques represents a very powerful tool for the performance analysis of multiprocessor systems and provides ways of investigating several extensions of the prototype architecture. Simulation results and measurements performed on the hardware prototype validate the analysis and show that the accuracy of the analytical results is excellent. View full abstract»

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  • Analytic Queueing Models for Programs with Internal Concurrency

    Page(s): 73 - 82
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    Analytic queueing models of programs with internal concurrency are considered. The program behavior model allows a process to spawn two or more concurrent tasks at some point during its execution. Except for queueing effects, the tasks execute independently of one another, and at the end of their execution, either wait for all of their siblings to finish execution or merge with the parent if all have finished execution. Two approximate solution methods for the performance prediction of such systems are developed, and results of the approximations are compared to those of simulations. The approximations are both computationally efficient and highly accurate. The gain in performance due to multitasking and multiprocessing is studied with a series of examples. View full abstract»

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  • Cost-Performance Bounds for Multimicrocomputer Networks

    Page(s): 83 - 95
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    Several interconnection structures for a distributed multimicrocomputer message-passing system are compared on the basis of cost and performance. Among the structures analyzed are buses, double rings, D-dimensional toroids, trees, cube-connected cycles, and chordal rings. Network cost is defined in terms of the number of network nodes and the unit cost of communication links and their associated connections. Simple asymptotic performance bounds are derived based on the bottleneck analysis of a queueing network. In contrast to the usual assumption of uniform message routing, the technique permits the introduction of a reference locality notion to the message routing behavior of network nodes. Finally, the cost, performance, and performance/cost functions are examined as the number of network nodes becomes very large. View full abstract»

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  • Multiserver Systems Subject to Breakdowns: An Empirical Study

    Page(s): 96 - 98
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    The tradeoffs between efficiency and reliability in M / M / N queueing systems subject to breakdowns are studied numerically. The dependence of the optimal number of servers on the system parameters is investigated under two different sets of assumptions about the pattern of breakdowns and repairs. View full abstract»

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  • IEEE copyright form

    Page(s): 98
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  • IEEE Computer Society Publications

    Page(s): 98
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  • Information for authors

    Page(s): 98
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Albert Y. Zomaya
School of Information Technologies
Building J12
The University of Sydney
Sydney, NSW 2006, Australia
http://www.cs.usyd.edu.au/~zomaya
albert.zomaya@sydney.edu.au