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IEEE Transactions on Computers

Issue 8 • Aug. 1982

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  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1982, Page(s): c1
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  • IEEE Computer Society

    Publication Year: 1982, Page(s): c2
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  • Computer Representation of Real Numbers

    Publication Year: 1982, Page(s):709 - 714
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2131 KB)

    Hwang's[1] model for the computer representation of real numbers is extended to explicitly distinguish between the representational system used to denote real numbers and the internal encoding of the digits of the representation in the computer memory. The encoding function can then be chosen to preserve certain properties of the real number system and to optimize the computer arithmetic in a sens... View full abstract»

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  • Window Random Access Protocols for Local Computer Networks

    Publication Year: 1982, Page(s):715 - 722
    Cited by:  Papers (20)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2364 KB)

    In this paper we consider a local computer network in which users communicate with each other over a single bus. We develop window search algorithms with which to implement random access protocols on the bus. Two protocols, one nonadaptive and the other adaptive are described. The maximum throughputs and throughput-delay tradeoffs are provided for both. These protocols show significant improvement... View full abstract»

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  • A Measurement Center for the NBS Local Area Computer Network

    Publication Year: 1982, Page(s):723 - 729
    Cited by:  Papers (33)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2819 KB)

    This paper describes a measurement center for the NBSNET, a distributed, broadcast local area computer network (LAN) at the National Bureau of Standards. A LAN measurement center allows careful testing and evaluation of a network under normal and varying user-defined conditions. The measurement center consists of three components: an artificial traffic generator, a monitoring system, and data anal... View full abstract»

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  • A Theory for Protocol Validation

    Publication Year: 1982, Page(s):730 - 738
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2834 KB)

    This paper introduces a simple algebra for the validation of communication protocols in message passing systems. The behavior of each process participating in a communication is first modeled in a finite state machine. The symbol sequences that can be accepted by these machines are then expressed in "protocol expressions," which are defined as regular expressions extended with two new operators: d... View full abstract»

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  • Delay and Throughput Analysis for Computer Communications with Balanced HDLC Procedures

    Publication Year: 1982, Page(s):739 - 746
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2325 KB)

    A series of explicit expressions are presented in this paper which describe the delay and throughput performances in computer communications with balanced HDLC procedures (HDLC ABM or X.25 LAPB). View full abstract»

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  • A Method for Equijoin Queries in Distributed Relational Databases

    Publication Year: 1982, Page(s):746 - 751
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3059 KB)

    A simple and efficient method for processing general equijoin queries in a distributed relational database is described. The query is first decomposed into a set of simple queries, each being involved with only one of the joining domains and its relevant equijoins. An extended version of Hevner and Yao's STRATEGY PARALLEL or STRATEGY SERIAL is then applied on each of them for generating transmissi... View full abstract»

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  • Automatic Generation of Symbolic Reliability Functions for Processor-Memory-Switch Structures

    Publication Year: 1982, Page(s):752 - 771
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (5160 KB)

    Calculation of the reliability of computer system architectures with built-in redundancy, such as multiprocessors, is gaining in importance. The task of computing the reliability function for arbitrary Processor-Memory-Switch (PMS) interconnection structures, however, is tedious and prone to human error. Existing reliability computation programs make one of two assumptions: • That the case a... View full abstract»

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  • Distributed Reconfiguration Strategies for Fault-Tolerant Multiprocessor Systems

    Publication Year: 1982, Page(s):771 - 784
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3687 KB)

    In this paper, we investigate strategies for dynamically reconfiguring shared memory multiprocessor systems that are subject to common memory faults and unpredictable processor deaths. These strategies aim at determining a communication page, i.e., a page of common memory that can be used by a group of processors for storing crucial common resources such as global locks for synchronization and glo... View full abstract»

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  • Some New Results About the (d, k) Graph Problem

    Publication Year: 1982, Page(s):784 - 791
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3585 KB)

    The (d,k) graph problem which is a stiu open extremal problem in graph theory, has received very much attention from many authors due to its theoretic interest, and also due to its possible applications in communication network design. The problem consists in maximizing the number of nodes n of an undirected regular graph (d,k) of degree d and diameter k. In this paper, after a survey of the known... View full abstract»

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  • A Canonical Bit-Sequential Multiplier

    Publication Year: 1982, Page(s):791 - 795
    Cited by:  Papers (22)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2251 KB)

    A serial multiplier suitable for VLSI implementation is discussed. The multiplier accepts binary operands supplied in a serial fashion, least significant bits first. The multiplier uses a canonical cell which allows calculation of a 2k length product with only k identical cells. These cells utilize the carry-save addition technique to provide a delay which exhibits only a first-order dependence on... View full abstract»

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  • A General-Purpose High-Speed Logical Transform Image Processor

    Publication Year: 1982, Page(s):795 - 800
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2440 KB)

    A new logical transform processor has been designed and its performance presented in this correspondence. The design incorporates the speed advantage of a locally parallel processor and yet has the capability of processing images of widely ranging dimension. Sixteen pixels are processed simultaneously using table lookup. Image size and neighborhood size are under program control of the host comput... View full abstract»

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  • A Method for Modulo-2 Minimization

    Publication Year: 1982, Page(s):800 - 801
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (452 KB)

    A minimization approach is presented for a modulo-2 expansion of a switching function. This method uses mixed polarity representation for the variables A local optimization procedure is presented which requires modest computation and is easily expanded. The procedure applied to the 32 DES select functions of six variables is reported. View full abstract»

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  • An Upper Bound for the Synthesis of Generalized Parallel Counters

    Publication Year: 1982, Page(s):802 - 805
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (482 KB)

    Recently, an algorithm has been developed for synthesizing generalized parallel counters (GPC's) with a network of smaller ones [11]. In this correspondence we obtain an upper bound q, for the number of levels q in the synthesis of GPC's. This upper bound generalizes and improves the values deduced by other authors in [13] and [14]. View full abstract»

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  • Call for Papers

    Publication Year: 1982, Page(s): 805
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  • IEEE Transcations on Computers Planned Special Issues

    Publication Year: 1982, Page(s): 805
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  • Advance Announcement... Tutorial Week West 82

    Publication Year: 1982, Page(s): 805
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  • IEEE Computer Society Publications

    Publication Year: 1982, Page(s): 805
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  • Call for Papers

    Publication Year: 1982, Page(s): 805
    Request permission for commercial reuse | PDF file iconPDF (142 KB)
    Freely Available from IEEE

Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org