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Computers, IEEE Transactions on

Issue 7 • Date July 1982

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Displaying Results 1 - 24 of 24
  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1982 , Page(s): c1
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  • IEEE Computer Society

    Publication Year: 1982 , Page(s): c2
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  • Editor's Notice

    Publication Year: 1982 , Page(s): 573 - 574
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  • Preface: Reliable and Fault-Tolerant Computing

    Publication Year: 1982 , Page(s): 575 - 577
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1706 KB)  

    THIS is the eighth Special Issue on this subject published by the IEEE TRANSACTIONS ON COMPUTERS. The title of this Special Issue now includes the word reliable to better reflect a broader perception of the field as expressed in the Chinese subtitle of the 10th International Symposium on Fault-Tolerant Computing (FTCS) held in Kyoto, Japan two years ago. It says: —to make (electronic compute... View full abstract»

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  • Test Generation Algorithms for Computer Hardware Description Languages

    Publication Year: 1982 , Page(s): 577 - 588
    Cited by:  Papers (45)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (4517 KB)  

    This paper proposes an extension of the D-algorithm to functions described in computer hardware description languages. The proposed extension is applicable to both procedural and nonprocedural languages. Methods of D-propagation through the basic constructs of these languages and test generation for circuits containing functions described in CHDL's are discussed. The fault modes considered are fun... View full abstract»

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  • Concurrent Error Detection in ALU's by Recomputing with Shifted Operands

    Publication Year: 1982 , Page(s): 589 - 595
    Cited by:  Papers (124)  |  Patents (8)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (2599 KB)  

    A new method of concurrent error detection in the Arithmetic and Logic Units (ALU's) is proposed. This method, called "Recomputing with Shifted Operands" (RESO), can detect errors in both the arithmetic and logic operations. RESO uses the principle of time redundancy in detecting the errors and achieves its error detection capability through the use of the already existing replicated hardware in t... View full abstract»

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  • Single Byte Error Correcting—Double Byte Error Detecting Codes for Memory Systems

    Publication Year: 1982 , Page(s): 596 - 602
    Cited by:  Papers (34)  |  Patents (17)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (2295 KB)  

    In a memory that uses byte-organized memory chips, each containing b (≥2) output bits, a single chip failure is likely to affect many bits within a byte. Single byte error correcting–double byte error detecting codes (SbEC–DbED codes) are used in this kind of memory system to increase reliability. View full abstract»

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  • Principles of Data Structure Error Correction

    Publication Year: 1982 , Page(s): 602 - 608
    Cited by:  Papers (3)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (3587 KB)  

    Error correction in robust data structures is a difficult problem. Several algorithms for correcting structural errors, in certain list and tree structures, are now known. These algorithms have been examined to determine common design features which may prove useful in the design of correction algorithms for other structures. This paper presents a summary of the algorithms studied and the design p... View full abstract»

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  • Fault-Tolerant Design for VLSI: Effect of Interconnect Requirements on Yield Improvement of VLSI Designs

    Publication Year: 1982 , Page(s): 609 - 616
    Cited by:  Papers (61)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (2766 KB)  

    In order to take full advantage of VLSI, new design methods are necessary to improve the yield and testability. Designs which incorporate redundancy to improve the yields of high density memory chips are well known. The goal of this paper is to motivate the extension of this technique to other types of VLSI logic circuits. The benefits and the limitations of on-chip modularization and the use of s... View full abstract»

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  • Formal Specification and Mechanical Verification of SIFT: A Fault-Tolerant Flight Control System

    Publication Year: 1982 , Page(s): 616 - 630
    Cited by:  Papers (21)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (4156 KB)  

    This paper describes the formal specification and proof methodology employed to demonstrate that the SIFT computer meets its requirements. The hierarchy of design specifications is shown, from very abstract descriptions of system function down to the implementation. The most abstract design specifications are simple and easy to understand, almost all details of the realization having been abstract... View full abstract»

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  • A Validation Technique for Tightly Coupled Protocols

    Publication Year: 1982 , Page(s): 630 - 636
    Cited by:  Papers (4)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (3630 KB)  

    For several years the authors have been part of an effort developing automated techniques for examining the syntax of protocols for the absence of various errors. Recently, we have turned our attention to trying to prove various functional properties of protocols used in ring-topology systems. Ring systems have a number of properties that distinguish them from the more general computer networks to... View full abstract»

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  • REBUS, A Fault-Tolerant Distributed System for Industrial Real-Time Control

    Publication Year: 1982 , Page(s): 637 - 647
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (3044 KB)  

    This paper presents a fault-tolerant distributed system designed for real-time control applications (REBUS), which is one of the research basis of the industrial real-time system MODUMAT 800. It is made up of functional units, i.e., programmable multiloop regulators and operator displays, linked together by a communication structure. The communication hardware consists of a set of serial bus inter... View full abstract»

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  • Closed-Form Solutions of Performability

    Publication Year: 1982 , Page(s): 648 - 657
    Cited by:  Papers (67)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (2705 KB)  

    If computing system performance is degradable, then as recognized in a number of recent studies, system evaluation must deal simultaneously with aspects of both performance and reliability. One approach is the evaluation of a system's "performability," which relative to a specified performance variable Y, generally requires solution of the probability distribution function of Y. In this paper we e... View full abstract»

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  • Derivation and Calibration of a Transient Error Reliability Model

    Publication Year: 1982 , Page(s): 658 - 671
    Cited by:  Papers (56)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (3701 KB)  

    In this paper a new modeling methodology to characterize failure processes in digital computers due to hardware transients is presented. The basic assumption made is that system sensitivity to hardware transient errors is a function of critical resources usage. The failure rate of a given resource is approximated by a deterministic function of time, depending on the average workload of that resour... View full abstract»

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  • A Hierarchical, Path-Oriented Approach to Fault Diagnosis in Modular Combinational Circuits

    Publication Year: 1982 , Page(s): 672 - 677
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1447 KB)  

    We present several extensions of the effect–cause analysis method [1] for fault diagnosis in combinational circuits. First, we extend the analysis to circuits consisting of interconnected modules that are assumed to be internal fault-free. To handle the situation in which the obtained response is incompatible with a fault domain restricted to the I/O pins of modules, we introduce a hierarchi... View full abstract»

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  • Totally Self-Checking Checker for 1-out-of-n Code Using Two-Rail Codes

    Publication Year: 1982 , Page(s): 677 - 681
    Cited by:  Papers (21)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1000 KB)  

    A new design for a totally self-checking 1-out-of-n checker is presented. A comparison with other existing methods [1], [10] is given. It is shown that for many practical values of n the new scheme requires less hardware and/or is faster than the other methods. The entire checker can be tested by applying all of the n possible 1-out-of-n inputs. View full abstract»

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  • Watchdog Processors and Structural Integrity Checking

    Publication Year: 1982 , Page(s): 681 - 685
    Cited by:  Papers (61)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1274 KB)  

    The use of watchdog processors in the implementation of Structural Integrity Checking (SIC) is described. A model for ideal SIC is given in terms of formal languages and automata. Techniques for use in implementing SIC are presented. The modification of a Pascal compiler into an SIC Pascal preprocessor is summarized. View full abstract»

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  • Self-Stabilizing Programs: The Fault-Tolerant Capability of Self-Checking Programs

    Publication Year: 1982 , Page(s): 685 - 689
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1151 KB)  

    Self-checking programs are programs which meet the following condition. For any legal input, either they return the correct output or they return a message indicating that the output may be incorrect. Self-checking programs are capable of recognizing irregular conditions in their state space and reporting it. Self-stabilizing programs are programs which, in addition to (or instead of) reporting ir... View full abstract»

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  • The Containment Set Approach to Upsets in Digital Systems

    Publication Year: 1982 , Page(s): 689 - 692
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1027 KB)  

    Fault analysis of digital systems is highly dependent upon the fault model employed. Much previous work utilizes fault models known to contain inaccuracies in order to permit mathematically tractable analysis. In this correspondence a new approach is taken which combines faults, hardware, and software together into one overall model. This new model is shown to be useful for the consideration of in... View full abstract»

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  • The Design of a Reliable Remote Procedure Call Mechanism

    Publication Year: 1982 , Page(s): 692 - 697
    Cited by:  Papers (19)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1624 KB)  

    In this correspondence we describe the design of a reliable Remote Procedure Call mechanism intended for use in local area networks. Starting from the hardware level that provides primitive facilities for data transmission, we describe how such a mechanism can be constructed. We discuss various design issues involved, including the choice of a message passing system over which the remote call mech... View full abstract»

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  • A Statistical Failure/Load Relationship: Results of a Multicomputer Study

    Publication Year: 1982 , Page(s): 697 - 706
    Cited by:  Papers (28)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (2309 KB)  

    In this correspondence we present a statistical model which relates mean computer failure rates to level of system activity. Our analysis reveals a strong statistical dependency of both hardware and software component failure rates on several common measures of utilization (specifically CPU utilization, I/O initiation, paging, and job-step initiation rates). We establish that this effect is not do... View full abstract»

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  • IEEE copyright form

    Publication Year: 1982 , Page(s): 706
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    Freely Available from IEEE
  • IEEE Computer Society Publications

    Publication Year: 1982 , Page(s): 706
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    Freely Available from IEEE
  • Information for authors

    Publication Year: 1982 , Page(s): 706
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    Freely Available from IEEE

Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org