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IEEE Transactions on Computers

Issue 4 • April 1982

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Displaying Results 1 - 21 of 21
  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1982, Page(s): c1
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  • IEEE Computer Society

    Publication Year: 1982, Page(s): c2
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  • Editor's Notice

    Publication Year: 1982, Page(s): 269
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  • On the Number of Permutations Performable by the Augmented Data Manipulator Network

    Publication Year: 1982, Page(s):270 - 277
    Cited by:  Papers (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2846 KB)

    The Augmented Data Manipulator (ADM) network has been proposed as an interconnection network for SIMD machines. As one measure for comparing the ADM network to multistage cube networks, the number of distinct data permutations performable in a single pass through the ADM is examined. Techniques are given to count the number of settings of any stage of the network which are permutations. Upper and ... View full abstract»

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  • Experience with Multiprocessor Algorithms

    Publication Year: 1982, Page(s):278 - 288
    Cited by:  Papers (33)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3441 KB)

    This paper presents results of experiments with parallel algorithms. Several versions of four different programs, each representing a class of applications, were tested. All the experiments were performed on Cm*,l a 50-processor computer with a hierarchical structure. The results show that when the structure of an algorithm corresponds well to the structure of the computer, a close-to-linear speed... View full abstract»

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  • Quotient Networks

    Publication Year: 1982, Page(s):288 - 295
    Cited by:  Papers (51)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3760 KB)

    A large-network algorithm solves a problem of size N on a network of N processors. We present a method for transforming certain large networks into quotient networks that emulate those large networks with fewer processors. Large-network algorithms are easily modified to execute on the quotient network. The emulations result in no loss in execution efficiency. Quotient networks allow algorithms to ... View full abstract»

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  • Analysis of Multiprocessors with Private Cache Memories

    Publication Year: 1982, Page(s):296 - 304
    Cited by:  Papers (36)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3093 KB)

    This paper presents an approximate analytical model for the performance of multiprocessors with private cache memories and a single shared main memory. The accuracy of the model is compared with simulation results and is found to be very good over a broad range of parameters. The parameters of the model are the size of the multiprocessor, the size and type of the interconnection network, the cache... View full abstract»

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  • Determining Fault Ratios in Multilevel Delayed Staging Storage Hierarchies

    Publication Year: 1982, Page(s):305 - 310
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2298 KB)

    A procedure to efficiently obtain fault ratios for all levels in multilevel delayed-staging (D-S) storage hierarchies without recurring to simulation runs for each configuration desired is presented. The procedure is based on the applicability of stack processing techniques to D-S configurations and requires simulation runs for two-level hierarchies only. View full abstract»

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  • Protection Against External Errors in a Dedicated System

    Publication Year: 1982, Page(s):311 - 317
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2207 KB)

    This paper deals with the protection of a dedicated subsystem against an erroneous environment. The inputs of the subsystem can be erroneous and the subsystem must be able to detect erroneous inputs and to recover from them. View full abstract»

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  • An Algebraic Model of Arithmetic Codes

    Publication Year: 1982, Page(s):318 - 321
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (783 KB)

    Arithmetic codes use a structured redundancy technique for binary number representation such that errors in an arithmetic operation of a digital computer can be detected or corrected. This correspondence studies the code structures by treating the set of redundant coded binary representations as a finite Abelian group. An algebraic model of arithmetic codes is developed, which shows that an arithm... View full abstract»

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  • An Autoscale Residue Multiplier

    Publication Year: 1982, Page(s):321 - 325
    Cited by:  Papers (35)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (850 KB)

    Dynamic range overflow is a serious problem in residue arithmetic systems. Contemporary overflow management schemes rely on inefficient scaling operations. In this correspondence a residue scaler is architectured which inhibits dynamic range overflow. The system uses the popular three moduli set {2n-1, 2n, 2n + 1}. Using a 4K memory model, practical 12-and 18-bit autoscalers are configured. An err... View full abstract»

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  • Comments on "An O(n) Parallel Multiplier with Bit-Sequential Input and Output"

    Publication Year: 1982, Page(s):325 - 327
    Cited by:  Papers (8)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (358 KB)

    For the realization of a bit-sequential multiplier with operands of length n, Chen and Willoner1 suggest a circuitry consisting of 2n identical modules. It is shown that if a slightly different arrangement of the modules is taken, the number of modules is reduced to n. Furthermore, the implementation in circuit form can be made more simple. View full abstract»

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  • Correction to "Error-Correcting Parsers for Formal Languages"

    Publication Year: 1982, Page(s):327 - 328
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (322 KB)

    In our earlier paper1 we proposed an algorithm S for error-correcting parsing of formal languages. It is found recently that two additional CS conditions and a routine for detecting infinite loop are required for the algorithm S. View full abstract»

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  • Loss of Significance in Floating Point Subtraction and Addition

    Publication Year: 1982, Page(s):328 - 335
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1166 KB)

    We study the loss of significant βits (Ξbase β digits) in floating point addition or subtraction. To do this, we calculate the conditional probability of a post-arithmetic normalization shift of m βits, given an exponent difference of k βits. The study is done for various bases β, under two different assumptions—that the operands are selected at random from the ... View full abstract»

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  • On the Generalized Binary System

    Publication Year: 1982, Page(s):335 - 338
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (645 KB)

    In this correspondence we derive algorithms for multioperand addition of Koren's generalized number system. A carry-lookahead adder for fast addition of two operands in generalized binary numbers is developed. Truncation errors for this type of representation are examined and rounding algorithms are presented to reduce these errors. View full abstract»

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  • Optimal BPC Permutations on a Cube Connected SIMD Computer

    Publication Year: 1982, Page(s):338 - 341
    Cited by:  Papers (135)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (719 KB)

    In this correspondence we develop an algorithm to perform BPC permutations on a cube connected SIMD computer. The class of BPC permutations includes many of the frequently occurring permutations such as matrix transpose, vector reversal, bit shuffle, and perfect shuffle. Our algorithm is shown to be optimal in the sense that it uses the fewest possible number of unit routes to accomplish any BPC p... View full abstract»

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  • IEEE Transactions on Computers Planned Special Issues

    Publication Year: 1982, Page(s): 342
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  • Call for Papers

    Publication Year: 1982, Page(s): 343
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  • IEEE Computer Society Press Checklist of New Titles December 1982

    Publication Year: 1982, Page(s): 343
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  • IEEE Computer Society Publications

    Publication Year: 1982, Page(s): 343
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  • Preliminary Program Ninth Annual International Symposium on Computer Architecture

    Publication Year: 1982, Page(s): 343
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org