IEEE Transactions on Computers

Issue 2 • Feb. 1982

Filter Results

Displaying Results 1 - 18 of 18
  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1982, Page(s): c1
    Request permission for commercial reuse | PDF file iconPDF (427 KB)
    Freely Available from IEEE
  • IEEE Computer Society

    Publication Year: 1982, Page(s): c2
    Request permission for commercial reuse | PDF file iconPDF (269 KB)
    Freely Available from IEEE
  • Automated Synthesis of Digital Hardware

    Publication Year: 1982, Page(s):93 - 109
    Cited by:  Papers (36)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4517 KB)

    This paper describes a portion of the Carnegie-Mellon University Design Automation (CMU-DA) research. This part involves the design and construction of a data-memory allocator, consisting of a set of algorithms and data structures which synthesize hardware at the register-transfer level from a behavioral description written in ISP. The allocator selects registers and data operators and interconnec... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design and Evaluation of a Synchronous Triangular Interconnection Scheme for Interprocessor Communications

    Publication Year: 1982, Page(s):110 - 118
    Cited by:  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2881 KB)

    A message oriented interprocessor communication network is proposed that utilizes a simple fixed algorithm to store-and-forward short messages over directed data lines. The modular design of the network permits message transmission along a variable number of processors. Simulations of the network's performance indicate that for appropriate message loads the network transmits messages in time propo... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Allocation of Operations in Distributed Database Access

    Publication Year: 1982, Page(s):119 - 129
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3180 KB)

    A model is developed for allocating the operations which are required by a transaction on a distributed database. The model considers the possibility of performing each operation distributedly, i.e., as a set of partial operations performed on different nodes. The criterion of optimality is the minimization of transmission costs. The model is formulated as a linear integer zero-one program. An exa... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Fault Diagnosis of MOS Combinational Networks

    Publication Year: 1982, Page(s):129 - 139
    Cited by:  Papers (17)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4353 KB)

    The increasing difficulties in testing large logic networks have generated the need for designing logic networks for testability. Computer algorithms for designing diagnosable metal oxide semiconductor (MOS) networks with and without fan-in, fan-out constraints were described in previous papers by the authors. In this two-part series, we discuss the testing of these designed networks. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Comparison of Universal-Logic-Module Realizations and Their Application in the Synthesis of Combinatorial and Sequential Logic Networks

    Publication Year: 1982, Page(s):140 - 147
    Cited by:  Papers (19)  |  Patents (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2386 KB)

    This paper surveys the six possible variants of the basic universal-logic-module, ULM.2, and considers possible circuit realizations for each. A comparison of these variants in terms of circuit complexity, propagation delay, and total number of input/output connections is pursued, and detailed statistics generated to compare with previously published optimum data using conventional NAND and NOR ga... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Parallel Algorithms to Set Up the Benes Permutation Network

    Publication Year: 1982, Page(s):148 - 154
    Cited by:  Papers (87)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2488 KB)

    A parallel algorithm to determine the switch settings for a Benes permutation network is developed. This algorithm can determine the switch settings for an N input/output Benes network in 0(log2N) time when a fully interconnected parallel computer with N processing elements is used. The algorithm runs in 0(N½) time on an N½× N½mesh-connected com... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Performance Analysis of the Implementation of Addressing Methods in Block-Structured Languages

    Publication Year: 1982, Page(s):155 - 163
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2684 KB)

    Variable accesses and scope rule enforcements represent a major part of the execution time of block-structured high-level language programs. The performance of a computer system largely depends on the implementation of the variable addressing mechanism. Several lexical level addressing mechanisms exist to reduce this overhead, including the well-known display mechanism and a proposal by Tanenbaum.... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Combinatorial Problem Concerning Processor Interconnection Networks

    Publication Year: 1982, Page(s):163 - 164
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1517 KB)

    The augmented data manipulator (ADM) [5] has been proposed as an interconnection scheme for microprocessors. In this note we show how the number of permutations achieved by the last stage of an n-node ADM may be derived from a Fibonacci series. This result was used in [1] to analyze the total number of permutations achieved by an entire ADM. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Application of Information Theory to Sequential Fault Diagnosis

    Publication Year: 1982, Page(s):164 - 170
    Cited by:  Papers (24)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1403 KB)

    In this correspondence we consider the problem of the construction of efficient sequential fault location experiments for permanent faults. The construction of optimum sequential experiments is an NP-complete problem and, therefore, a heuristic approach for the design of near-optimum sequential experiments is considered. The approach is based on information theoretic concepts and the suggested alg... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Architecture for VLSI Design of Reed-Solomon Encoders

    Publication Year: 1982, Page(s):170 - 175
    Cited by:  Papers (11)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1009 KB)

    In this correspondence the logic structure of a universal VLSI chip called the symbol-slice Reed-Solomon (RS) encoder chip is presented. An RS encoder can be constructed by cascading and properly interconnecting a group of such VLSI chips. As a design example, it is shown that a (255, 223) RS encoder requiring around 40 discrete CMOS IC's may be replaced by an RS encoder consisting of four identic... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Fast Haar Transform Algorithms

    Publication Year: 1982, Page(s):175 - 177
    Cited by:  Papers (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (603 KB)

    In this correspondence the implementations of fast Haar transforms are examined. Previous algorithms are described and compared to a new implementation called the in place algorithm. By performing the transform in place and limiting the amount of data movement, the algorithm attains greater memory efficiency and speed than other known algorithms. Index Terms-Efficient algorithm, Haar transform, in... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • IEEE Transactions on Computers Planned Special Issues

    Publication Year: 1982, Page(s): 177
    Request permission for commercial reuse | PDF file iconPDF (81 KB)
    Freely Available from IEEE
  • IEEE Computer Society Press Checklist of New Titles December 1981

    Publication Year: 1982, Page(s): 177
    Request permission for commercial reuse | PDF file iconPDF (246 KB)
    Freely Available from IEEE
  • Call for Papers

    Publication Year: 1982, Page(s): 177
    Request permission for commercial reuse | PDF file iconPDF (186 KB)
    Freely Available from IEEE
  • IEEE Computer Society Publications

    Publication Year: 1982, Page(s): 177
    Request permission for commercial reuse | PDF file iconPDF (182 KB)
    Freely Available from IEEE
  • Advance Announcement... Tutorial Week East 82

    Publication Year: 1982, Page(s): 177
    Request permission for commercial reuse | PDF file iconPDF (1965 KB)
    Freely Available from IEEE

Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org