IEEE Transactions on Computers

Issue 12 • Dec. 1982

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Displaying Results 1 - 18 of 18
  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1982, Page(s): c1
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  • IEEE Computer Society

    Publication Year: 1982, Page(s): c2
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  • Direct Implementation of Asynchronous Control Units

    Publication Year: 1982, Page(s):1133 - 1141
    Cited by:  Papers (56)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3200 KB)

    The "one-hot" row assignment for asynchronous circuits, in which every row in a flow table has exactly one of the feedback variables that equals the value 1, provides a straightforward method for circuit synthesis. Once a flow table has been constructed, the state equations can be directly written, without requiring any procedure to ensure a race-free assignment. Furthermore, it can implement any ... View full abstract»

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  • A Two-Level Microprogrammed Multiprocessor Computer with Nonnumeric Functions

    Publication Year: 1982, Page(s):1142 - 1156
    Cited by:  Papers (2)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4694 KB)

    A two-level microprogrammed multiprocessor system, MUNAP, along with its support software has been developed as a research vehicle for solving nonnumeric and associated problems. The MUNAP system provides highly parallel and distributed functions for nonnumeric processing, such as variable length word addressing, data permutation at the microprogram level, and bit operation and field handling at t... View full abstract»

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  • Experience with the Parallel Solution of Partial Differential Equations on a Distributed Computing System

    Publication Year: 1982, Page(s):1157 - 1164
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2242 KB)

    It is of interest to determine whether loosely coupled multiprocessors can be profitably used for the solution of larger numerical problems. We present here a performance evaluation of the gain obtained by solving partial differential equation systems on such an architecture. The experimental setting is an LSI 11 based multimicroprocessor system using a fiber optics local area network designed and... View full abstract»

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  • Fault Diagnosis in Synchronous Sequential Circuits Based on an Effect–Cause Analysis

    Publication Year: 1982, Page(s):1165 - 1172
    Cited by:  Papers (24)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2581 KB)

    In this paper we present a new approach to fault diagnosis in sequential circuits based on an effect–cause analysis. This represents an extension of our previous work dealing with combinational circuits [1]. The main tool of our approach is the Deduction Algorithm, which deduces internal values in the circuit under test based upon the test results. The deduced values are used for fault diagn... View full abstract»

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  • Lower Bounds on Crosspoints in Concentrators

    Publication Year: 1982, Page(s):1173 - 1179
    Cited by:  Papers (27)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2347 KB)

    Lower bounds on the required number of crosspoints in concentrators, a class of interconnection networks, are given. The lower bounds are obtained from a straightforward necessary condition on the number of crosspoints in sparse crossbar full capacity concentrators. Because this condition must be satisfied by all full capacity concentrators embedded in more general concentrators, the general neces... View full abstract»

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  • Comparative Performance Analysis of Single Bus Multiprocessor Architectures

    Publication Year: 1982, Page(s):1179 - 1191
    Cited by:  Papers (48)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4882 KB)

    Markovian models are developed for the performance analysis and comparison of several single bus multiprocessor architectures. Processors are assumed to cooperate in a message passing fashion, and messages are exchanged through common memory areas. Four architectures are considered in this paper which differ in the location of the common memory modules. Contention for shared resources is modeled a... View full abstract»

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  • The Parallel Enumeration Sorting Scheme for VLSI

    Publication Year: 1982, Page(s):1192 - 1201
    Cited by:  Papers (39)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2728 KB)

    We propose a new parallel sorting scheme, called the parallel enumeration sorting scheme, which is suitable for VLSI implementation. This scheme can be introduced to conventional computer systems without changing their architecture. In this scheme, sorting is divided into two stages, the ordering process and the rearranging one. The latter can be efficiently performed by central processing units o... View full abstract»

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  • Routing Schemes for the Augmented Data Manipulator Network in an MIMD System

    Publication Year: 1982, Page(s):1202 - 1214
    Cited by:  Papers (50)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4020 KB)

    There have been many multistage interconnection networks proposed in the literature for interconnecting the processors that comprise large parallel processing systems. In this paper, the use of the Augmented Data Manipulator and Inverse Augmented Data Manipulator multistage networks in the MIMD mode of operation is considered. A tag based routing scheme which allows distributed control of either n... View full abstract»

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  • Partitioned Matrix Algorithms for VLSI Arithmetic Systems

    Publication Year: 1982, Page(s):1215 - 1224
    Cited by:  Papers (60)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2476 KB)

    A new class of partitioned matrix algorithms is developed for possible VLSI implementation of large-scale matrix solvers. Fast matrix solvers are higherly demanded in signal/image processing and in many real-time and scientific applications. Only a few functional types of VLSI arithmetic chips are needed for submatrix computations after partitioning. This partitioned approach is not restricted by ... View full abstract»

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  • An Optimal Illumination Region Algorithm for Convex Polygons

    Publication Year: 1982, Page(s):1225 - 1227
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (690 KB)

    For the convex polygon P having n vertices entirely contained in a convex polygon K having m vertices, an optimal algorithm with running time O(n + m) is presented to compute and name regions in the boundary of K from which it is possible to illuminate the exterior of P. It is also shown that this illumination region algorithm can be used to improve the worst case O(nm) running time of a related t... View full abstract»

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  • Bandwidth of Crossbar and Multiple-Bus Connections for Multiprocessors

    Publication Year: 1982, Page(s):1227 - 1234
    Cited by:  Papers (82)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1133 KB)

    In this paper we compare the effective bandwidth in a multiprocessor with shared memory using as interconnection networks the crossbar or the multiple-bus. We consider a system with N processors and N memory modules, in which the processor requests to the memory modules are independent and uniformly distributed random variables. We consider two cases: in the first the processor makes another reque... View full abstract»

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  • 1982 Index IEEE Transactions on Computers Vol. C-31

    Publication Year: 1982, Page(s): 1234
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  • Call for Papers 1983 Trends and Applications Conference

    Publication Year: 1982, Page(s): 1234
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  • Call for Papers Eighth Data Communications Symposium—1983

    Publication Year: 1982, Page(s): 1234
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  • IEEE Computer Society Publications

    Publication Year: 1982, Page(s): 1234
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  • 1983 International Conference on Parallel Processing

    Publication Year: 1982, Page(s): 1234
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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org