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IEEE Transactions on Computers

Issue 11 • Nov. 1982

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Displaying Results 1 - 18 of 18
  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1982, Page(s): c1
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  • IEEE Computer Society

    Publication Year: 1982, Page(s): c2
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  • Introduction: Parallel and Distributed Processing

    Publication Year: 1982, Page(s):1033 - 1035
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2949 KB)

    THE GROWTH of interest in parallel and distributed processing in the last decade has been explosive. It will doubtlessly continue unabated, being the only approach to increasing the speed and power of computing systems whose ultimate limits, by fundamental physical laws or well-established theory, are not yet definable. Some of the papers that follow in this Special Issue on Parallel and Distribut... View full abstract»

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  • The ETH-Multiprocessor Empress: A Dynamically Configurable MIMD System

    Publication Year: 1982, Page(s):1035 - 1044
    Cited by:  Papers (20)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (5579 KB)

    The MIMD multiprocessor EMPRESS (ETH-Multiprocessor) to be described was built in order to study the performance of MIMD architectures in general, and particularly in the field of simulation problems. By means of a dynamically configurable architecture in combination with a powerful processor intercommunication principle, the system is able to handle two-stage parallelism: several independent subt... View full abstract»

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  • Design of HM2p—A Hierarchical Multimicroprocessor for General-Purpose Applications

    Publication Year: 1982, Page(s):1045 - 1053
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3153 KB)

    This paper presents a tree-structured multiprocessor called the hierarchical multimicroprocessor (HM2p), each node of which is composed of a cluster of processor modules (PM's), common memory, DMA interface, switches, communication lines, and a data processor associated with it. The HM2p consists of two different hierarchies, one for data processing and the other for data distribution, which provi... View full abstract»

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  • Wavefront Array Processor: Language, Architecture, and Applications

    Publication Year: 1982, Page(s):1054 - 1066
    Cited by:  Papers (152)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3563 KB)

    This paper describes the development of a wavefront-based language and architecture for a programmable special-purpose multiprocessor array. Based on the notion of computational wavefront, the hardware of the processor array is designed to provide a computing medium that preserves the key properties of the wavefront. In conjunction, a wavefront language (MDFL) is introduced that drastically reduce... View full abstract»

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  • Minimization of Interprocessor Communication for Parallel Computation

    Publication Year: 1982, Page(s):1067 - 1075
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2846 KB)

    This paper is concerned with minimizing the delay due to data communication during the execution of a parallel algorithm on an SIMD computer with a two-way circular unit-shift interconnection network. Algorithms are developed which determine, for a given parallel procedure, the order of computation within that procedure, for every parallel arithmetic expression, the alignment of operands for every... View full abstract»

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  • A Practical Algorithm for the Solution of Triangular Systems on a Parallel Processing System

    Publication Year: 1982, Page(s):1076 - 1082
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2273 KB)

    An algorithm is presented for a more efficient and implementable solution of triangular systems on a parallel (SIMD) computer which requires 0(log (N)) fewer processing cycles than the best previous results, where N is the system size. We will also show that the data can be accessed and aligned in the same order of time using as many memory units as processors and Ω networks for data alignmen... View full abstract»

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  • Effects of Cache Coherency in Multiprocessors

    Publication Year: 1982, Page(s):1083 - 1099
    Cited by:  Papers (50)  |  Patents (29)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3939 KB)

    In many commercial multiprocessor systems, each processor accesses the memory through a private cache. One problem that could limit the extensibility of the system and its performance is the enforcement of cache coherence. A mechanism must exist which prevents the existence of several different copies of the same data block in different private caches. In this paper, we present an in-depth analysi... View full abstract»

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  • Queueing Network Models for Parallel Processing with Asynchronous Tasks

    Publication Year: 1982, Page(s):1099 - 1109
    Cited by:  Papers (46)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4318 KB)

    Computer performance models of parallel processing systems in which a job subdivides into two or more tasks at some point during its execution are considered. Except for queueing effects, the tasks execute independently of one another and do not require synchronization. An approximate solution method is developed and results of the approximation are compared to those of simulations. Bounds on the ... View full abstract»

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  • Pin Limitations and Partitioning of VLSI Interconnection Networks

    Publication Year: 1982, Page(s):1109 - 1116
    Cited by:  Papers (30)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2722 KB)

    Multiple processor interconnection networks can be characterized as having N' inputs and N' outputs, each being B' bits wide. A major implementation constraint of large networks in the VLSI environment is the number of pins available on a chip, Np. Construction of large networks requires partitioning of the N' * N' * B' network into a collection of N * N switch modules with each input and output p... View full abstract»

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  • Memory Interference in Synchronous Multiprocessor Systems

    Publication Year: 1982, Page(s):1116 - 1121
    Cited by:  Papers (50)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1212 KB)

    Synchronous N-processor systems with M shared memories are considered. Memory interference is modeled for processor request rates between 0 and 1 per memory cycle. Two probability-based models and one queueing-based model are summarized from prior literature. A new steady-state flow model is introduced. This steady-state model is most accurate overall. The queueing model is somewhat more accurate ... View full abstract»

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  • On the Analysis and Synthesis of VLSI Algorithms

    Publication Year: 1982, Page(s):1121 - 1126
    Cited by:  Papers (101)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1321 KB)

    This correspondence is concerned with the development of algorithms for special-purpose VLSI arrays. The approach used in this correspondence is to identify algorithm transformations which modify favorably the index set and the data dependences, but perserve the ordering imposed on the index set by the data dependences. Conditions for the existance of such transformations are given for a class of ... View full abstract»

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  • Modeling Unusual Behavior of Parallel Algorithms

    Publication Year: 1982, Page(s):1126 - 1130
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1019 KB)

    A probabilistic model of a class of parallel programs is used to investigate the counterintuitive behavior observed for some parallel algorithms. Two main points are made: 1) it may, in general, be beneficial to consider using more logical processes than physical processors in a parallel algorithm; and 2) results from order statistics are useful tools in analyzing parallel systems. View full abstract»

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  • 1983 International Conference on Parallel Processing

    Publication Year: 1982, Page(s): 1130
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    Freely Available from IEEE
  • Call for Papers 1983 Trends and Applications Conference

    Publication Year: 1982, Page(s): 1130
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  • IEEE Computer Society Publications

    Publication Year: 1982, Page(s): 1130
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  • Advance Announcement... Tutorial Week East 83

    Publication Year: 1982, Page(s): 1130
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org