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IEEE Transactions on Computers

Issue 9 • Date Sept. 1981

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Displaying Results 1 - 19 of 19
  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1981, Page(s): c1
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  • IEEE Computer Society

    Publication Year: 1981, Page(s): c2
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  • Guest Editors' Comments

    Publication Year: 1981, Page(s):617 - 618
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1836 KB)

    MULTIPLE-VALUED logic has been the subject of considerable study during the past decade [1]-[3]. Indeed, there has been an annual symposium devoted exclusively to the subject since 1971. The Proceedings of these annual symposia provide a historical perspective to the developments in multiple-valued logic. Initially, researchers were most concerned with such problems as the determination of functio... View full abstract»

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  • The Prospects for Multivalued Logic: A Technology and Applications View

    Publication Year: 1981, Page(s):619 - 634
    Cited by:  Papers (99)  |  Patents (24)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4569 KB)

    Advances in multiple-valued logic (MVL) have been inspired, in large part, by advances in integrated circuit technology. Multiple-valued logic has matured to the point where four-valued logic is now part of commercially available VLSI IC's. Besides reduction in chip area, MVL offers other benefits such as the potential for circuit test. This paper describes the historical and technical background ... View full abstract»

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  • Multiple-Valued Decomposition of Generalized Boolean Functions and the Complexity of Programmable Logic Arrays

    Publication Year: 1981, Page(s):635 - 643
    Cited by:  Papers (39)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2400 KB)

    Generalized Boolean functions are shown to be useful for the design of programmable logic arrays (PLA's), and the complexity of three types of PLA's is obtained by the theory of multiple- valued decomposition. A two-level PLA consists of an AND array and an OR array, and they are cascaded to perform a two-level AND-OR circuit. A PLA with decoders consists of decoders, an AND array, and an OR array... View full abstract»

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  • Multiple-Valued Logic Charge-Coupled Devices

    Publication Year: 1981, Page(s):644 - 652
    Cited by:  Papers (30)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3834 KB)

    A new method to implement multiple-valued logic in large scale integrated circuits is introduced. The data are represented by discrete amounts of charge in a charge-coupled device. In this paper the design principles and realizations in four-valued logic of a minimum and maximum circuit, a complement circuit, a literal a successor, and an adder are presented. Also, the designs of a binary-to-quate... View full abstract»

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  • Synthesis of Discrete Functions Using I2L Technology

    Publication Year: 1981, Page(s):653 - 661
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2310 KB)

    Algebraic methods for designing multiple-valued I2L circuits are presented. A new operation, namely the truncated difference, is introduced and proved to be an efficient tool for both analyzing and synthesizing circuits. View full abstract»

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  • SEC-DED Nonbinary Code for Fault-Tolerant Byte-Organized Memory Implemented with Quaternary Logic

    Publication Year: 1981, Page(s):662 - 666
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (801 KB)

    Byte-organized memory requires an error control scheme which can handle errors involving one or several entire bytes. A special parallel nonbinary single error correction and double error detection SEC-DED block code is constructed by dynamic programming. This code is optimum in the sense that it lends itself to a simple and high-speed hardware implementation either in binary or in quaternary logi... View full abstract»

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  • On the Design of 4-Valued Digital Systems

    Publication Year: 1981, Page(s):666 - 671
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1088 KB)

    The availability of 4-valued I2L circuits presents a new perspective for digital systems designers. This correspondence explores several aspects of digital system design using 4-valued logic elements. An approach to designing the ith stage of an ALU employing these elements is presented. The realization of rudimentary ALU operations is shown using the T-gate as a universal building block System de... View full abstract»

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  • Tree Structured Sequential Multiple-Valued Logic Design from Universal Modules

    Publication Year: 1981, Page(s):671 - 674
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (819 KB)

    A design procedure is presented for realizing multiple-valued sequential logic functions as tree structured networks of sequential universal logic modules (SULM's). Both definite and nondefinite finite state machines can be realized using this approach. The SULM employed is a multiple-valued multiplexer-flip-flop cascade that can be efficiently implemented in multiple-valued technologies. View full abstract»

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  • Representation of Multivalued Functions Using the Direct Cover Method

    Publication Year: 1981, Page(s):674 - 679
    Cited by:  Papers (26)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1036 KB)

    An efficient method for representing multivalued functions is described. The method employs an algorithm which generates an efficient cover for a given function "directly," i.e., without resorting to the intermediate step of creating a table of prime implicants. Data are presented to show that the covers generated are as efficient in terms of cover size as prime implicant based methods. More impor... View full abstract»

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  • Diagnosis of Systems with Asymmetric Invalidation

    Publication Year: 1981, Page(s):679 - 690
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3930 KB)

    This paper is concerned with system diagnosis through analysis of a set of diagnostic test results. It is assumed that a faulty unit may cause one or more tests on a good unit to fail, but may not cause tests on faulty units to pass (asymmetric invalidation). The system model employed is quite general; each test may be invalidated by any one of a set of units, and each test may completely test mor... View full abstract»

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  • Design of High-Speed Digital Divider Units

    Publication Year: 1981, Page(s):691 - 699
    Cited by:  Papers (9)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2660 KB)

    The division operation has proved to be a much more difficult function to generate efficiently than the other elementary arithmetic operations. This is due primarily to the need to test the result of one iteration before proceeding to the next. The technique described in this contribution reduces the iteration time by the use of a redundant quotient representation, which avoids the need to complet... View full abstract»

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  • Synthesis of Generalized Parallel Counters

    Publication Year: 1981, Page(s):699 - 703
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1842 KB)

    Synthesis of generalized equal column parallel counters from smaller ones is presented. The notation used for a general counter is (n × N; d), where n is the number of input columns, N is the number of input bits in each column, and d = s · n (s = 2, 3,···) is the number of bits in the output word. View full abstract»

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  • Planned Special Issues IEEE Transactions on Computers

    Publication Year: 1981, Page(s): 704
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  • Call for Papers

    Publication Year: 1981, Page(s): 705
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  • Students in Computer Science and Engineering!

    Publication Year: 1981, Page(s): 705
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  • IEEE Computer Society Publications

    Publication Year: 1981, Page(s): 705
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  • Advance Announcement... Tutorial Week West 81

    Publication Year: 1981, Page(s): 705
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org