IEEE Transactions on Computers

Issue 8 • Aug. 1981

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  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1981, Page(s): c1
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  • IEEE Computer Society

    Publication Year: 1981, Page(s): c2
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  • The Expression Processor: A Pipelined, Multiple- Processor Architecture

    Publication Year: 1981, Page(s):525 - 536
    Cited by:  Papers (5)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (3639 KB)

    A nem multiple-processor architecture is described that can exploit the instruction level concurrency in numerical processing tasks. The expression processor contains multiple processing elements (PE's), which can be configured either as an SIMD [8] array or as an expression tree pipeline. An expression tree is the parse tree conctructed by a compiler from an arithmetic or logical expression. The ... View full abstract»

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  • Tree Search in Major/Minor Loop Magnetic Bubble Memories

    Publication Year: 1981, Page(s):537 - 545
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (2524 KB)

    In this paper we analyze various search schemes in a major/minor loop bubble memory. Specifically, we study balanced tree search, one-sided height-balanced tree search, and one-sided K-Keight-balanced tree search. Two parameters are of interest in the present framework, namely, the number of comparisons and the amount of record movement required for a search. One-sided height- balanced tree search... View full abstract»

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  • Interference Analysis of Shuffle/Exchange Networks

    Publication Year: 1981, Page(s):545 - 556
    Cited by:  Papers (27)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (4348 KB)

    The use of shuffle/exchange (S/E) interconnection networks in multiprocessor systems has been proposed for several applications. In order to evaluate the potential performance and reliability of such systems, the effects of conflicts involving switch and memory contention should be determined. This paper presents a discrete Markov chain model to study the effects of such contention for S/E network... View full abstract»

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  • On Closedness and Test Complexity of Logic Circuits

    Publication Year: 1981, Page(s):556 - 562
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (3520 KB)

    The concept of closedness of a set of logic functions under stuck-type faults is introduced. All sets of logic functions closed under stuck-type faults are classified. For the sets of logic functions closed under stuck-type faults, the test complexity and the universal test sets are considered. It is shown that for each class of linear functions, OR functions, and AND functions, both the minimum n... View full abstract»

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  • A Functional Approach to Testing Bit-Sliced Microprocessors

    Publication Year: 1981, Page(s):563 - 571
    Cited by:  Papers (63)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (3003 KB)

    Bit-sliced microprocessors are representative of an important class of LSI components that can be interconnected in a regular way to construct many useful types of digital systems. This paper develops an analytic test generation methodology for bit-sliced systems. A formal model C for a 1-bit bit-sliced microprocessor is defined which has the main features of many commercially available microproce... View full abstract»

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  • A Layout System for the Random Logic Portion of an MOS LSI Chip

    Publication Year: 1981, Page(s):572 - 581
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (3075 KB)

    The random logic portion of an MOS LSI chip intended mainly for a calculator is constructed of an array of MOS complex gates, each composed of an MOS ratioless circuit with a multiphase clocking system, and occupies ordinarily a considerable part of chip area. In this paper a layout system for this portion of an LSI chip is described, which is constructed on the basis of heuristics for a set of in... View full abstract»

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  • An Information Theoretic Approach to Digital Fault Testing

    Publication Year: 1981, Page(s):582 - 587
    Cited by:  Papers (52)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1254 KB)

    The concepts of information theory are applied to the problem of testing digital circuits. By analyzing the information throughput of the circuit an expression for the probability of detecting a hardware fault is derived. Examples are given to illustrate an application of the present study in designing efficient pattern generators for testing. View full abstract»

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  • Fault Diagnosis in a Boolean n Cube Array of Microprocessors

    Publication Year: 1981, Page(s):587 - 590
    Cited by:  Papers (145)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (884 KB)

    Fault- tolerant characteristics of a Boolean n cube array of microprocessors are analyzed. Connectivity properties of the network graph are used to show that n processor or link failures are required to isolate a processor. For processor failures the network is shown to be n (one step) diagnosable. A testing algorithm is presented which can diagnose up to n processor failures. View full abstract»

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  • Speed-Efficiency-Complexity Tradeoffs in Universal Diagnosis Algorithms

    Publication Year: 1981, Page(s):590 - 596
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1160 KB)

    Expressions are derived for the average number of steps. required (speed) and the average number of fault-free units replaced (efficiency) when universal diagnosis algorithms are applied to systems of various degrees of interconnection (complexity). Specifically, two algorithms proposed by Smith [4] are considered. It is shown, for example, that there is a clear tradeoff between the two algorithms... View full abstract»

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  • Stored State Asynchronous Sequential Circuits

    Publication Year: 1981, Page(s):596 - 600
    Cited by:  Papers (12)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (963 KB)

    A method is described for realizing asynchronous sequential circuits in a manner analogous to the stored state method for synchronous sequential circuits. The method simplifies the process of constructing asynchronous sequential circuits, allows utilization of existing MSI parts, and avoids the necessity for concern with races or hazards. View full abstract»

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  • Reliability Measure of Hardware Redundancy Fault-Tolerant Digital Systems with Intermittent Faults

    Publication Year: 1981, Page(s):600 - 604
    Cited by:  Papers (21)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1121 KB)

    While significant results are available which allow estimation of reliability measure for systems with permanent faults, no generally applicable results are available for intermittent (transient) faults. Methods are presented here which allow reliability evaluation for systems with both intermittent and permanent faults. Two reliability measures, instantaneous and durational reliabilities, are def... View full abstract»

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  • Syndrome-Testability Can be Achieved by Circuit Modification

    Publication Year: 1981, Page(s):604 - 606
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (655 KB)

    In [1] and [2] Savir developed many facets of syndrome-testing (checking the number of minterms realized by a circuit against the number realized by a fault-free version of that circuit) and presented evidence showing that syndrome-testing can be used in many practical circuits to detect all single faults. In some cases, where syndrome-testing did not detect all single stuck-at-faults, Savir showe... View full abstract»

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  • Syndrome-Testing of " Syndrome-Untestable" Combinational Circuits

    Publication Year: 1981, Page(s):606 - 608
    Cited by:  Papers (19)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (674 KB)

    In [1] and [2] a method of designing syndrome-testable combinational circuits was described. It was shown that, in general, syndrome-testable combinational circuits require some pin-penalty and maybe some logic for producing the testable design. View full abstract»

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  • Comments on "Parallelism and Representation Problems in Distributed Systems"

    Publication Year: 1981, Page(s):608 - 609
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (458 KB)

    The above paper by Flynn and Hennessy' contains the following errors on page 1082. View full abstract»

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  • An Algebra for Switching Circuits

    Publication Year: 1981, Page(s):609 - 613
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (792 KB)

    Using Boolean algebra to formulate and manipulate switching circuit representations is commonplace. However, because standard logic elements are not confined to the basic functions of the algebra, AND, OR, and NOT, conventional Boolean algebra is less practical than it could be. View full abstract»

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  • Call for Papers Special Issue on Computer Architecture for Pattern Analysis and Image Database Management

    Publication Year: 1981, Page(s): 613
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  • Call for Papers

    Publication Year: 1981, Page(s): 613
    Request permission for commercial reuse | |PDF file iconPDF (62 KB)
    Freely Available from IEEE
  • Call for Papers

    Publication Year: 1981, Page(s): 613
    Request permission for commercial reuse | |PDF file iconPDF (148 KB)
    Freely Available from IEEE
  • IEEE Computer Society Publications

    Publication Year: 1981, Page(s): 613
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  • Call for Papers Special Issue on Reliable and Fault-Tolerant Computing

    Publication Year: 1981, Page(s): 613
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org