IEEE Transactions on Computers

Issue 12 • Dec. 1981

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  • IEEE Transactions on Computers - Table of contents

    Publication Year: 1981, Page(s): c1
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  • IEEE Computer Society

    Publication Year: 1981, Page(s): c2
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  • In Memoriam

    Publication Year: 1981, Page(s): 909
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  • An Optimal Algorithm for Determining the Visibility of a Polygon from an Edge

    Publication Year: 1981, Page(s):910 - 914
    Cited by:  Papers (79)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2168 KB)

    In many computer applications areas such as graphics, automated cartography, image processing, and robotics the notion of visibility among objects modeled as polygons is a recurring theme. This paper is concerned with the visibility of a simple polygon from one of its edges. Three natural definitions of the visibility of a polygon from an edge are presented. The following computational problem is ... View full abstract»

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  • Delay Analysis of Broadcast Routing in Packet-Switching Networks

    Publication Year: 1981, Page(s):915 - 922
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2339 KB)

    Broadcast addressing is the capability to send a packet from a source node to all other nodes in the network. Store-and-forward, packet-switching networks are not inherently designed to carry broadcast packets, and broadcasting has to be implemented by some sort of routing algorithm. In this paper, the source based forwarding algorithm is considered. With this algorithm, a spanning tree is defined... View full abstract»

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  • Hypertree: A Multiprocessor Interconnection Topology

    Publication Year: 1981, Page(s):923 - 933
    Cited by:  Papers (74)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3242 KB)

    A new interconnection topology for incrementally expansible multicomputer systems is described, which combines the easy expansibility of tree structures with the compactness of the n-dimensional hypercube. The addition of n-cube links to the binary tree structure provides direct paths between nodes which have frequent data exchange in algorithms such as sorting and fast Fourier transforms (FFT's).... View full abstract»

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  • PASM: A Partitionable SIMD/MIMD System for Image Processing and Pattern Recognition

    Publication Year: 1981, Page(s):934 - 947
    Cited by:  Papers (156)  |  Patents (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (5540 KB)

    PASM, a large-scale multimicroprocessor system being designed at Purdue University for image processing and pattern recognition, is described. This system can be dynamically reconfigured to operate as one or more independent SIMD and/or MIMD machines. PASM consists of a parallel computation unit, which contains N processors, N memories, and an interconnection network; Q microcontrollers, each of w... View full abstract»

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  • An Approach for Error Detection and Error Correction in Distributed Systems Computing Numerical Functions

    Publication Year: 1981, Page(s):947 - 953
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3552 KB)

    We consider methods of error detection and/or error correction in software and hardware of a distributed system computing values of numerical functions. These methods are based on software and hardware redundancy for the computation of additional check functions. The check functions are easily derived for any given multiplicity of errors. The redundancy does not depend on the number of processors ... View full abstract»

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  • Self-Diagnosing Cellular Implementations of Finite-State Machines

    Publication Year: 1981, Page(s):953 - 959
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3650 KB)

    Cellular spaces are shown to possess properties favorable to reconfiguration. As a first step in the direction of reconfigurable cellular spaces, this paper demonstrates the implementation of arbitrary finite-state machines in self-diagnosing cellular spaces. The results cover single cell failures caused by erroneous state transitions or by erroneous outputs. One of the attractive features of the ... View full abstract»

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  • The Lens Interconnection Strategy

    Publication Year: 1981, Page(s):960 - 965
    Cited by:  Papers (24)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2415 KB)

    In this paper we describe a new family of topologies for interconnecting many identical processors to form an MIMD multiprocessor. It extends to arbitrarily many processors while keeping the number of neighbors of any one processor fixed. We show that this family behaves very well with respect to uniformity of bus load, simplicity of routing algorithms, and distance between processors. View full abstract»

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  • Digital Convolution Algorithm for Pipelining Multiprocessor Systems

    Publication Year: 1981, Page(s):966 - 973
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2334 KB)

    The calculation of convolution (noncyclic) of two finite sequences is a fundamental operation in digital signal processing. In this paper we derive two digital convolution algorithms which are efficient in terms of number of multiplications and also structurally simple, and hence suitable for implementations in a tree machine or in a VLSI chip where a simple geometry of circuit layout is highly de... View full abstract»

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  • A Graph Model for Pattern-Sensitive Faults in Random Access Memories

    Publication Year: 1981, Page(s):973 - 977
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2259 KB)

    This correspondence generalizes Hayes' recent ideas for generating an optimal transition write sequence which forms the "backbone" of his algorithm for testing semiconductor RAM's for pattern-sensitive faults. The generalization, presented in graph theoretic terms, involves two sequential steps. The frmst step results in assigning of a "color" to each memory cell. In the second step, each color is... View full abstract»

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  • A Layout for the Shuffle-Exchange Network with O(N2/log3/2N) Area

    Publication Year: 1981, Page(s):977 - 982
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1140 KB)

    A layout for the shuffle-exchange network with O(N2/log3/2N) area is described. The layout combines ideas proposed by Thompson, Hoey, and Leiseron, and Preparata and Vuillemin. An interesting feature of the layout is that both the shuffle and the exchange edges have the same average length. View full abstract»

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  • A March Test for Functional Faults in Semiconductor Random Access Memories

    Publication Year: 1981, Page(s):982 - 985
    Cited by:  Papers (110)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1026 KB)

    A test procedure requiring 14 N operations to detect functional faults in semiconductor random access memories (RAM's) is given. It is shown that the proposed test procedure detects modeled types of functional faults if only one type of fault is present in the RAM under test. The test procedure given belongs to a class of tests called march tests. It is proved that any march test requires at least... View full abstract»

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  • Comments on "Design of a Dynamically Programmable Logic Gate"

    Publication Year: 1981, Page(s):986 - 987
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (420 KB)

    Suarez, Chang, and Adam have recently disclosed an input-programmable logic configuration, with four input terminals to provide the specified range of function capability. Here we contrast the disclosure with an alternative line of universal logic element research, and indicate that three input terminals only are required in this alternative approach. View full abstract»

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  • Authors' reply2

    Publication Year: 1981, Page(s): 987
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  • Defect Level as a Function of Fault Coverage

    Publication Year: 1981, Page(s):987 - 988
    Cited by:  Papers (251)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (350 KB)

    This correspondence presents a single equation relating the defect level of LSI chips to the yield and stuck-at-fault coverage with some assumptions. It is assumed that the faults occur randomly on the chips, which implies no clustering. This concept is extended to modules on boards. View full abstract»

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  • Test-Experiments for Detection and Location of Intermittent Faults in Sequential Circuits

    Publication Year: 1981, Page(s):989 - 995
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1630 KB)

    Practical solutions have not been obtained from the previous papers addressing the problem of testing intermittent faults in sequential circuits. Existing methods are only suitable for small sequential circuits. This correspondence presents a new technique to design test-experiments for intermittent faults which can conveniently be used for relatively more complex synchronous sequential circuits. View full abstract»

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  • The Weighted Syndrome Sums Approach to VLSI Testing

    Publication Year: 1981, Page(s):996 - 1000
    Cited by:  Papers (40)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1012 KB)

    With the advent of VLSI, testing has become one of the most costly, complicated, and time consuming problems. The method of syndrome- testing is applicable toward VLSI testing since it does not require test generation and fault simulation. It can also be considered as a vehicle for self-testing. In order to employ syndrome-testing in VLSI, we electronically partition the chip into macros in test m... View full abstract»

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  • 1981 Index IEEE Transactions on Computers Vol. C-30

    Publication Year: 1981, Page(s): 1000
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  • IEEE Transactions on Computers Planned Special Issues

    Publication Year: 1981, Page(s): 1000
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  • Call for Papers

    Publication Year: 1981, Page(s): 1000
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  • IEEE Computer Society Publications

    Publication Year: 1981, Page(s): 1000
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  • Advance Announcement... Tutorial Week East 82

    Publication Year: 1981, Page(s): 1000
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org